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Rating Stats for

Greg

Rating
1564.37 (4,856th)

Reputation
13,439 (10,732nd)

Page: 1 2 3 ... 12

Title	Δ
reg instantiate with 1 in verilog	0.00
Nested conditional operator / mux syntax	+0.39
multiple modules different name same ports	0.00
SystemVerilog concatenation assignment is incorrect	+2.01
Verilog getting output as 'x' after running the test branch	0.00
How do I pass multiple clocking blocks with different polariy from...	+2.02
Operands in verilog	+2.38
Writing to simulator log file without writing to terminal	0.00
Why does my bidirectional port only give my output but 8'hxx fo...	0.00
Warning: Inferring latch for variable 'w_addra_t' (in Veril...	+0.42
4 bit 4:1 mux structural modelling in verilog using veriwave	0.00
Flip flop testbench shows incorrect values	-1.64
Bit slicing with variable width in SystemVerilog	-1.16
Icarus verilog: reg show; cannot be driven by primitives or continu...	0.00
verilog bit select of concatenation	+0.05
Linting: Comparing Verilog Parameter and Constant String	-0.18
Splitting inout array into multiple inout signals in verilog	-1.97
Why the constrained randomization of UVM does not work?	0.00
How do I fix error: near "[": syntax error, unexpected &#...	+0.33
Quartus does not allow using a Generate block in Verilog	-2.32
Passing a single row of a 2d array as an input to a module in verilog	0.00
Unable to get output in Verilog simulation of digital clock	0.00
How to prevent ModelSIM from stopping during simulation?	0.00
I am writing a SystemVerilog Testbench for a module that models a s...	0.00
Multiple bits gates	0.00
Can't create symbole file for module because port has unsupport...	+1.04
Verilog HDL always & case errors	-0.11
How to get latch with blocking assignment?	+0.40
SV: Error llegal combination of procedural drivers	+1.58
Does subtraction need less resource than comparison symbol in veril...	0.00
Include guards in SystemVerilog	-2.20
How can I assign module arguments in Verilog?	+0.41
Verilog: Always statement, trigger on positive edge for 3 bit varia...	0.00
Why I'm keep getting error in the output signal?	0.00
FF/Latch has a constand value of 0 because of parameter	0.00
DPI-C and SystemVerilog External Compilation flow issue	-0.07
Unexpected Behavior of tri1 with multiple driver	0.00
how implement store byte and store half-word in realistic approach	+1.62
How does one initialize an integer array in Verilog?	-0.09
What is the difference between $signed and signed' in verilog?	0.00
Can someone please explain why this causes a combinational feedback...	0.00
systemverilog module namespaces	-0.40
Implementing a for loop in systemverilog	0.00
How to convert this SystemVerilog sim to Verilog	0.00
SystemVerilog memory with 32'hFFFFFFFF top address fails	+2.14
FileIO in System Verilog for floating point numbers	0.00
What is the maximum wire bit-width in verilog/system verilog	-1.00
How to give input to a task	+0.09
increment operation in Systemverilog Vivado not working as expected	0.00
Verilog case statement is always true	0.00