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Greg

Rating
1564.37 (4,856th)

Reputation
13,439 (10,732nd)

Page: 1 2 3 4 ... 12

Title	Δ
Changing clocking block clock polarity on the fly	0.00
Indexing array of instances and interfaces	0.00
Asynchronous reset warning issue	0.00
Generate block with many nested cases	0.00
How to fix my current MIPS 32 SCP Register File's clock/data er...	0.00
Verilog expand each bit n times	-1.28
Can we initialize variables with "nets", instead of a con...	0.00
First if statement in an always block always evaluated to true init...	0.00
Which is the synthesized digital circuit for this [verilog] mux wit...	-1.82
How to make Serial BCD code input in verilog	-0.10
Turning matrix to array in verilog 2005	0.00
How to use generate on a block with SV interfaces	0.00
Cannot match operand(s) in the condition to the corresponding edges...	0.00
Why do I get a syntax error on the testbench?	0.00
SystemVerilog Assertions: Once A is asserted, A remains high until...	+1.73
Converting finite state machine diagram into verilog code	+0.41
Verilog: initialization in hierarchical design	-0.61
how to concatenate a row buffer into a register in Verilog	+0.40
(Verilog) Testbench Wait	0.00
Creating verilog code from schematic	0.00
How to avoid Inferred latches in ASM chart verilog?	-0.54
Error in task: syntax error in assignment statement l-value	0.00
Change the top level's variables inside the called modules in v...	-0.68
Verilog handling input wires	0.00
How to model bidirectional transport delay	0.00
Verilog: Changing multiple states in one case statement	+1.53
case statement with multiple cases doing same operation	+0.12
Verilog seems to default an option in a case statement	0.00
Why verilog simulators model net delay as inertial delay rather tha...	-0.47
Verilog modulus operator for wrapping around a range	0.00
how to concatenate bit with a string in system verilog?	0.00
Why does system verilog max() and min() functions return a queue an...	-0.57
Multi Bit Logic Gate	0.00
Issues programming an FPGA by comp sci major, unexpected output	+0.41
Verilog: How to assign the an inout to another inout?	-2.49
latch warning due to case statement with codeword from ps2 keyboard...	0.00
Delays in for loop	-1.92
System Verilog Testbench waveforms no data	0.00
In DPI-C, what data types to be used for internal variables?	+0.36
What is the purpose of register model in UVM?	+2.08
parameterized class queue in sv	0.00
hex value in verilog generate for loop	+0.37
Is it possible to access signal in unencrypted module instance insi...	+2.10
Modelsim - Object not logged & no signal data while simulating...	0.00
systemverilog dynamically accessing subarray	0.00
Verilog strange simulation results post synthesis	+0.40
What is a LINT/synthesis safe statement to throw an error at compil...	+1.06
Reading a text file in verilog HDL	0.00
Verilog input error	+0.41
What exactly is the difference between the Xilinx warnings XST:1710...	0.00