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1505.96 (123,352nd)

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3,927 (42,729th)

Page: 1 ... 9 10 11 12

Title	Δ
Verilog assigning multiple reg's or wire's to the same value	+5.13
Getting the "Invalid module instantiation" in my FIR Veri...	0.00
static and dynamic linking using gcc	+3.29
C++ Separated static field for each derived class	-3.27
JavaFX ImagePane resize Bad Quality	+0.26
How to clear bits of unsigned char array in C?	+2.04
How to give a delay of 1 clock cycle in a combinational block verilog	0.00
mask some bits in a vector based on a different vector	0.00
Code generation using preprocessor macros	0.00
#define used with operators	-3.05
Generating a set of valid parentheses in C++	-1.52
Why does the function have to return a char * but not a char array?	-3.54
How to write a verilog code in two-always-block style with multiple...	0.00
Split string to words after a given symbol in java	-2.85
how to log my program every 10 seconds	+4.37
109 bit tree comparator with generate and for loop	+0.26
Confusion about stack growth and addressing	+1.05
Display characters matched in strings	-0.86
How to dump verilog compiled lines from a verilog file with many if...	0.00
Create bitmask based on a pattern as constexpr	-3.61
SystemVerilog - With an enum can you have a range?	+4.39
C++ sizeof C-style string / char array - optimization	-1.47
Signed binary multiplication and signed binary division	+0.20
Using inouts with wand	0.00
C++ nested class instances	-3.80
calculating worst case delay in verilog simulation	0.00
Is delete allowed to modify its parameter?	-1.01
What is the purpose of this module?	+5.11
Type of an object changing during construction	+1.25
Pointers with multiple asterisk?	+4.46
Arrays of interface instances in SystemVerilog with parametrized nu...	-0.80
How to turn off submodule of a C++ library based on preprocessor de...	0.00
fpga programming using verilog	-4.04
write on invalid address to RAM in VHDL, Verilog, sim behaviour	+0.64
multiple return values Vulkan C++ function header	0.00
Optionally descend a nested struct	+0.92
Alternate signals for test bench without manually typing out all ti...	-3.61
awk to extract lines in file that contain matching pattern and vari...	+2.48
Allocate variable type and size array inside function (c++)	+0.28
Verilog [cross module resolution error] when expanding the definiti...	0.00
regex matching dp	-3.80
Add elements dynamically to an array in JAVA	+0.21
main function argument not define default then how compiler call ma...	0.00
C++ - fopen return null pointer	0.00
Verilog: Implementation Using Primitive Modules vs. Bit-wise Operat...	+4.26
Pattern Generator (verilog)	0.00
Verilog strange simulation results post synthesis	-1.41
where does a c++ function puts return value	-3.08
What is the difference between flush and endl?	+3.78
How to print tree by level	0.00