StackRating

An Elo-based rating system for Stack Overflow

Home | About | Stats and Analysis | Get a Badge

Rating Stats for

Giampietro Seu

Rating
1516.81 (39,321st)

Reputation
645 (222,463rd)

Page: 1

Title	Δ
Driving record elements through procedures from different processes...	-2.70
Modelsim: Analog Waveform of grouped signals	+3.82
Verilog: if without else inside clocked always block creates regist...	0.00
VHDL: formal port 'portName' has no actual or default value	0.00
How to change element index of array?	-4.26
What's the equivalent of Verilog tilde operator "~" i...	+3.78
How to add '0' to between every 2 bits of a logic vector	0.00
vhdl modelsim return "1" or "0" status to comma...	+2.55
This for loop displays only the last entry of the student record	-2.22
"Readline called past the end of file" error VHDL	0.00
If sensitivity list in VHDL is not synthesizable, why does it gives...	-4.03
How to sort an nx3 numpy array by column(s) but it remembers the da...	-0.31
How to get the correct number of distinct combination locks with a...	-1.76
List of python to make plot	0.00
VHDL truncation leads to malfunction of an implemented FIR Filter	0.00
How to assign to the address of a pointed pointer the value stored...	+3.72
how to print and get down one row in c	-2.27
RGB to YUV conversion equation	0.00
Slice from a matrix to a vector in VHDL2008	+3.93
'Opt_Design Error' in Vivado when trying Run Implementation	0.00
how can i specify a generic array of std_logic_vectors?	0.00
Complex if statements are not simulatable	-3.71
Verilog LED Blinking no syntax errors. why it is not blinking	+3.77
Nonlinear behavior of function run time	+4.69
spawns some threads and performs a calculation in the thread worker...	0.00
How to use "std_logic" after package/package body declara...	+4.09
why print 'hello' three times in my centos?	-2.44
How to move the numerical calculation part from VHDL code to C can...	0.00
Linked list with structures using command line arguments	+4.43
Why do incomplete if statements create latches during synthesis in...	+0.01
In VHDL, How to implement two tristate buffers driving the same pin...	+3.35
Implementing a short pulse signal triggered by a push button on a S...	0.00
Trying to finish adder need if statement to change carry	0.00
How does this function print the correct HEX of the given argument	+2.39
How to make this VHDL 'for' loop work with no error on mode...	0.00
Pylint: how to prevent prints	0.00