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Rating Stats for

Charles Steinkuehler

Rating
1494.88 (4,278,360th)

Reputation
2,965 (57,037th)

Page: 1 2

Title	Δ
VHDL: Correctly way to infer a single port ram with synchronous read	+4.02
Implementing open collector and 'z' data type	+2.39
VHDL decimation(?) of data in specific way	0.00
Why am I getting an Inferred Latch Error?	0.00
IF statement doesn't work in a vhdl process	0.00
Process in VHDL	0.00
error while using the resize function in vhdl	0.00
How to shift an std_logic_vector to the right without truncating th...	0.00
Compilation of vhdl code	0.00
How can I edit a pinmux for BeagleBone Black on linux kernel 3.17?	+0.10
Type Error in VHDL	-3.79
Comparing bits from std_logic_vector	0.00
How to place component parts on RAM on chip	+0.33
Driving GPIO pins shared with SRAM in VHDL	+0.08
PRBS Generator module in VHDL	-3.52
I want to check if std_logic_vector contains negative integer	-3.58
state transition falling edge	0.00
Displaying Two Different Variables On The 7 segment LED Display wit...	-0.22
VHDL: Counting input values not registering final input	-0.03
VHDL - AND operation between vector and bit	+0.60
VHDL code does not synthesize	+0.56
Array literals in VHDL	+0.13
VHDL swap two values	0.00
VHDL XST not synthesizing correctly	-1.83
Undesiderated 1-bit latch (VHDL)	0.00
When to use "case" and when to use "with select"	+0.28
Why does my VHDL code have latches?	+0.17
Why cant 'and' have such operands in this context?	+4.04
Where should a constant be declared?	-3.96
Unexpected if vhdl	+0.28
VHDL Casting Error	-0.03
How to use user defined types in a vhdl submbodule?	0.00
VHDL when else doesnt work	0.00
Altera Qsys and top level entity with array of std_logic_vector	-1.96
Altera Qsys and top level entity with array of std_logic_vector	+4.04
How to "slice" an std_logic_vector in VHDL?	0.00
VHDL function does not compile	+0.07
VHDL setting constant data in RAM	0.00
FF/Latch and other warnings	-3.67
Found 1-bit latch for signal and constant value warnings	-0.15
Sine LUT VHDL wont simulate below 800 hz	0.00
D Flip Flop in VHDL	0.00
possible to reference attributes of function return type?	0.00
How to detect compiler	+0.29
Structural 4 bit ring counter with D flip flop. VHDL / GHDL	0.00
Loop for a Case	+0.02
Syntax error with process	0.00
VHDL and FPGA's	+4.24
Pipeline Accumulator VHDL	+0.05
Implementing an Accumulator in VHDL	+4.06