StackRating

An Elo-based rating system for Stack Overflow

Home | About | Stats and Analysis | Get a Badge

Rating Stats for

Tim

Rating
1575.75 (3,409th)

Reputation
31,130 (3,869th)

Page: 1 2 3 4 ... 15

Title	Δ
How to generate delay in verilog for synthesis?	+0.39
Multiplication matrix and store sram or sdram	-0.11
Multiplying 2D arrays in Verilog	+0.41
Piggybacking to UVM error	0.00
Best way to sum many things on an FPGA	+0.38
Fundamental Verilog Concepts	0.00
Verilog questions on 2's complement and left roate	0.00
Configure ModelSim simulation to display text	0.00
writing a ripple carry adder in verilog	-0.58
optimization choices with slice LUT and slice registers in Xilinx F...	0.00
Carry/auxiliary flag functions in x86 ALU	0.00
MS Excel - Sum of multiple cells if the cell contains "X"	-0.11
If statement and assiging wires in Verilog	+0.15
For loop in always block	0.00
Verilog Parallel Check and Assignment Across Dissimilar Sized Shift...	0.00
Is there a ifx-elsex statement in Verilog/SV like casex?	-1.51
circular shift left of indexes - verilog	0.00
cannot use an input for if statement in Verilog	+0.39
Verilog how to use input and output of submodule inside always block	+0.39
Simple Verilog example for a LED Switch?	-0.58
Verilog always block statement	+0.37
Why do I get an "Incompatible types at assignment" error...	0.00
Verilog, logic OR-ing an entire array	0.00
Verilog error: Register is illegal in left-hand side of continuous...	+0.39
Unexpected warnings in Xilinx	0.00
concatenate inputs in verilog	0.00
How to create 2's Complement Adder in Verilog?	0.00
Verilog - always sensitivity list	+0.40
How to do "AND" stencil in OpenGL?	0.00
Verilog - individual output arrays	-0.11
Registers in module Instantion	0.00
How to define and assign Verilog 2d Arrays	+0.45
What is always followed by #(...) pound mean in Verilog?	0.00
Verilog why is [NumberOfBits-1:0] and what is it actually doing	+0.39
How does a simple state machine look in Verilog?	-0.11
How to execute a for loop over multiple clock cycles?	0.00
how can I reduce mux size	0.00
vim: delete all words on line except last	-0.66
array and multiplexer in Verilog	-0.39
Verilog changing a value of a variable	0.00
Event control in always @(posedge clk)	-0.06
How to write a test bench for ports of multidimentional arrays	0.00
Counter based memory array in Verilog	0.00
Issue with Logic in Verilog	+1.80
How to generate sinc wave using verilog	0.00
Simulator showing wrong input	0.00
how to nullify register in system verilog	-0.91
Optimize this comparator for better synthesis	+0.40
Are there compiler directives for specifying the type of adder synt...	+1.81
Verilog Multiple Signals Change In Sensitivity List of an Always Bl...	+0.40