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Rating Stats for

Kevin Thibedeau

Rating
1525.72 (23,052nd)

Reputation
2,732 (61,845th)

Page: 1 2 3

Title	Δ
VHDL initialize signal with maximum value of type	0.00
Phantomjs font rendering issue in svg file	0.00
Using PangoCairo with PyGObject API	0.00
how to connect LVDS signals coming from test equipment to fpga virt...	0.00
Using usb keyboard on FPGA Boards (VHDL)	0.00
Use of conv_integer in VHDL	+0.49
Are muxes more "expensive" than other logic?	-1.76
Modelsim simulate clock divider	0.00
VHDL: DELAY_LENGTH vs. $NATURAL_TIME	0.00
How to make the library work work?	-0.05
Testbench and unconstrained std_logic_vector	0.00
How to get rid of scale factor from CORDIC	-3.82
How to wait for Modelsim Simulations to complete before proceeding...	-1.28
VHDL error - STD logic type is not known	0.00
Inbuilt Adders used in FPGA	0.00
Definition for "string" in C	-3.85
debounce code of a mecanique switch in vhdl	0.00
Check if modulo of a number exists in a tuple	-3.19
i2c comunication in vhdl, an X bit when going form master ack to fi...	+0.21
VHDL: How to declare a variable width generic	+3.82
Strings containing duplicate characters for if statements in Python	0.00
'ascii' codec can't encode error when reading using Pyt...	0.00
2's compliment input and using vhdl library for signed input	+3.84
how to avoid delay in the output of simple process statement in VHDL	+3.89
Sorting a sub-array in an array according to some condition - Python	+0.53
Python Hex String Check If Bit is set	0.00
VHDL declare an array of std_logic_vector with variable size	0.00
VHDL modify one signal with mutiple clock	0.00
VHDL Parametric case	+3.82
Are renamed clocks synchronous?	+0.30
Batch file that calls a vsim command	+4.35
Comparing reals in VHDL	+4.25
unsigned to integer conversion VHDL	0.00
VHDL Hamming code for correcting error	-0.38
what is the blocks that i need to make memory 16*16 bit slot in VHDL?	0.00
Can someone help me find where I get stuck in a loop VHDL	0.00
How to fix clock hold in this code?	+4.01
VHDL synthesis of if statements without elsif and else condition	-1.60
Generating a generic delay package in VHDL	0.00
Quartus II : can't determine definition of operator ""...	0.00
Is there a way to assert that all signals in a design are initializ...	0.00
Sign function in VHDL	+3.91
(Tcl?) Script for running modelsim with testbench as parameter from...	0.00
Determine if design element exists in library with script	0.00
Components not being instantiated properly in VHDL generate statement	0.00
Adding 2 std_logic_vector in variable type VHDL	0.00
What VHDL libraries to use for decimal modulus	-4.01
Which signal in the sensitivity list triggers the process	+4.31
Create Chan In TCL for specific app	+4.97
How to get real type ratio between two time values?	+4.02