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Rating Stats for

Brian Magnuson

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1505.59 (129,883rd) 		Reputation
1,208 (131,703rd)
Page: 1
Title Δ
how to use Verilog mode AUTOINST? 0.00
Verilog concatenation with 0 bit length 0.00
Verilog, testing for Zero flag 0.00
Use tasks in always @* blocks +3.96
SystemVerilog: $urandom call inside conditional expression 0.00
Counting of different channels diverge and jumps 0.00
Verilog Increment Decrement counter using Altera Board 0.00
Include files in verilog: compilation options for modelsim +0.92
Recommended order of input and output ports in Verilog module decla... +4.49
Priority 8-to-3 encoder in Verilog (case, casex) 0.00
chisel3 arithmetic operations on Doubles -2.56
Does time delay in a sequential logic circuit block have a influenc... +1.84
Signed binary multiplication and signed binary division -0.20
I wish to display a line with a negative slope in system verilog th... 0.00
How to display a 14 bit output onto a 2 digit display? +4.20
Generate Block Compile Time If-Else Parameterized +0.09
Asynchronous FIFO Design 0.00
Difference between Synchronous and Asynchronous reset in Flip Flops 0.00
ERROR : Verilog system function $value$plusargs invoked as task.Ret... -3.53
How to ignore specific unused wires in Verilog? 0.00
Avoiding code repetition in Verilog +0.44
Is it possible to design a smaller FPGA on an FPGA? 0.00
CPLD Pins not being driven -3.82
Make HTTP Request from Verilog 0.00
template error in Xilinx 0.00
Generate If Statements in Verilog +4.11
Why does this C# program will run out of memory in a 64-bits comput... +4.71
verilog multidimensional array 0.00
verilog array referencing 0.00
Why are the outputs of this pseudo random number generator (LFSR) s... -3.20
iterating with a for loop in Python +0.99
Is it ok to force value on an input port in Systemverilog? -3.91
Finding fewest bits to store an int in 2s complement -2.66
verilog counter implementation unexpected behaviour +4.06
Incrementing a counter variable in verilog: combinational or sequen... 0.00
Using an if else condition in a generate block in Verilog 0.00
How can I use a prepared module in a loop in Verilog? 0.00
Timing issue in Verilog -0.04
C program links to wrong version of function -4.30