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baldyHDL

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1500.70 (432,415th) 		Reputation
1,292 (124,338th)
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Weird behaviour of finite state machine in VHDL 0.00
Addition of 2 numbers from keyboard using spartan 3 (vhdl) 0.00
Division on the last outputs 0.00
How to map with a 163 bit number with a 1-bit number? 0.00
signal x is array (1 to n) of type - VHDL 0.00
Trying to implement spi bus in vhdl -0.10
getting undefined symbol error, even thought the variable is define... +4.10
VHDL procedure causes undefined signals where identical code outsid... 0.00
VHDL pattern detector +2.01
how to declare two dimensional arrays and their elements in VHDL 0.00
I am writing a code to generate a PWM wave in VHDL but I am getting... 0.00
VHDL execution order? 0.00
Variables in 2 processes dont work out for me 0.00
VHDL: Traffic Light State Machine not Synthesizing 0.00
Define "enum"-type depending on generics +4.18
simulating a VHDL FSM with ModelSim 0.00
compare two clock signals 0.00
Infinite amount of time when trying to synthesize behavioral VHDL c... +0.80
7-segment display in VHDL? 0.00
discrete cosine transform using VHDL +0.81
cyclically 8 bit shifter ,VHDL +0.18
VHDL FSM set unit input and use output in same state 0.00
VHDL initialize vector (the length is not a multiple of 4) in hex +2.31
Type of "variable" incompatible with type of "variab... +4.20
8 bit ALU for microprocessor +0.30
VHDL Product of two natural numbers 0.00
Generating Single Port ROM on Spartan 6 using Xilinx ISE Design Suite -0.99
VHDL: on converting numbers? real to std_logic_vector -3.76
vhdl string to font 5x7 0.00
vhdl string to font 5x7 0.00
VHDL - How to adding 1 to STD_LOGIC_VECTOR? -3.38
VHDL programming +0.19
Mealy and Moore implementations in verilog -1.91
When to use what types +0.16
VHDL read generic default value +0.17
VHDL library for basic elements -3.28
VHDL bit aggregation +0.02
add png-image into VHDL documentation 0.00
How to use more than one delay counter in same process in VHDL +0.73
high frequency from low frequency clock +4.10
VHDL infinite loop 0.00
VHDL Shift with Concatenation 0.00
Combinational division in HDL 0.00
VHDL Syntax error in IF-ELSE block of finite state machine +0.62
VHDL shift operators? +0.66
VHDL Simulation Error Releated to Register Bank 0.00
Wires are not connected in the RTL 0.00
Can't resolve multiple constant drivers VHDL Error +2.48
ps/2 keyboard interface VHDL 0.00
variable assignment and synthesizable code +0.08