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Rating Stats for

Karan Shah

Rating
1435.95 (4,534,948th)

Reputation
1,248 (128,185th)

Page: 1 2 3

Title	Δ
Bit slicing in verilog	+4.51
SystemVerilog - Value of member class are not updated	0.00
UVM: create a task that gets called every 100 or so cycles for all...	-0.83
Verilog can't output square wave if assigned to one variable bu...	0.00
SystemVerilog - go over all the child member from the parent class	0.00
what's the return value of unblock assignment in verilog?	0.00
unexpected output from signal processing structure module	0.00
Virtual sequence class plan	-3.59
Verilog CMOS OR gate error	0.00
How to write to inout port and read from inout port of the same mod...	+4.75
"Multiple Constant Drivers" Error Verilog with Quartus Pr...	-1.15
uvm_reg peek function takes long time to return	0.00
Using uvm_reg_hw_reset_seq	0.00
How to change and manipulate clock in SystemVerilog	+4.66
How to declare input/output ports dynamically (show/no show) in ver...	+0.89
Compute e^x for float values in System Verilog?	0.00
Driving a internal wire in my module from my interface task	-2.75
How to check if all possible combination of elements in an array gr...	0.00
Timing analysis for shortest path for hold violation	+0.87
Can we use ternary operator inside an always block? Is MOD(%) opera...	0.00
Initialize Block RAM with file which contain ASCII data	0.00
can someone explain fork and loop in system verilog?	-2.82
Bit-vector sign extension in simulink	0.00
SystemVerilog over vcs saving simulation state and rewinding	0.00
Creating a 2-D net array in verilog	+0.83
How to assert a property is false at every clock cycle?	-3.52
Execution of Generate Block	+0.38
How can you add systemverilog class variables or class members to w...	-3.56
The different between factory, config_dg, and resources_db	0.00
Error (10219): Verilog HDL Continuous Assignment error at Mux.v(19)...	-3.10
How to initial unpacked array with another unpacked array	-3.57
Verilog: Is the following code going to make a race condition?	-3.00
SystemVerilog- How to write a constructor with initialization?	-3.05
Avoiding support code for SVA sequence to handle pipelined transact...	-3.01
SVA assume/assertions for continuous data input	+4.30
What is the difference between using an initial block vs initializi...	-2.54
What's the advantage of bit over reg in systemverilog?	-3.44
Integer input ports in verilog simillar to vhdl?	+0.44
Comparing simulation performance	-2.37
systemverilog: use of unsized & unbased literal in comparison	-3.23
systemverilog -> Passing parameters from an interface that insta...	-3.53
Verilog Program Counter with branching	+0.26
assertion for holding the reset for a long time	+0.16
"If" inside an always OR condition in the sensitivity lis...	0.00
How can I create a dynamic array with different random values in ra...	-1.61
Meaning of [->1] in system verilog property definition	-3.85
Verilog - shift register queue or circular queue?	0.00
How can I OR every element in two dimensional array in one clock cy...	-3.27
Issue with SystemVerilog for loop having non-blocking assignment?	-3.62
systemVerilog Nested Fork	-1.50