StackRating

An Elo-based rating system for Stack Overflow
Home   |   About   |   Stats and Analysis   |   Get a Badge
Rating Stats for

CliffordVienna

Rating
1513.74 (49,692nd) 		Reputation
5,589 (29,382nd)
Page: 1 2 3
Title Δ
modify iCE40 bitstream to load new block RAM content 0.00
iceprog - Can't find iCE FTDI USB device 0.00
iceprog .. Can't find iCE FTDI USB device (Linux permission iss... 0.00
Find and Replace an operation in Verilog using Yosys 0.00
How do I get a list of unconnected cell ports using the Yosys RTLIL... 0.00
visualizing yosys output not working 0.00
Is it possible to create a simulation waveform from yosys output 0.00
timing analysis report for ASIC synthesis 0.00
C standard compliant way to access null pointer address? +1.37
Netlist validation using Yosys 0.00
error while executing abc in yosys (win32) 0.00
Can You Reduce K-Independent Set to 2-SAT 0.00
How to simplify compound assignments in yosys 0.00
gate level parsing using yosys 0.00
Yosys Can't open include file 0.00
Generate TIE cells with Yosys? 0.00
FSM export using Yosys 0.00
How can I compile C code only for the RV32I base integer instructio... 0.00
Lattice iCE40-HX8K Board - UART 0.00
Can/does SigMap produce canonical output? 0.00
Use iopadmap with extra clock port 0.00
What is required to target a new device? -0.08
Does yosys preserve port ordering? 0.00
How does the Yosys ConstEval API work? 0.00
What is the reset address for Rocket chip? 0.00
System instruction working 0.00
How to execute yosys passes from an LLVM pass? 0.00
Error reg. Liberty file reading at ABC stage 0.00
RISCV dissassembly options numeric and no-aliases +3.97
What is a good "template" Yosys synthesis script? 0.00
2 Questions about Risc-V-Privileged-Spec-v1.7 -4.18
Calling variadic template function with no args failing 0.00
Linux Device Tree (DTS): i2c device on USB-I2C bridge 0.00
parse dimacs CNF file python 0.00
How range overflow affects the simulation and synthesis? 0.00
Verilog asynch mem in Xilinx 0.00
Can I change the order of argument evaluation in clang? 0.00
Counter Design with D Flip-Flop 0.00
Accessing members of composite sorts (data types) in SMT-LIBv2 0.00
When is using whitespace for readability NOT allowed? +1.05
Converter from SAT to 3-SAT +0.30
Going back to initial statement on reset in verilog -4.11
Is explicit type conversion necessary in A a = (A) b; +1.38
real world SAT instances 0.00
What is .arm in assembly code ? -4.15
Converting to (not from) ipython Notebook format 0.00
least square approximation: how this matrix calculation equation is... 0.00
Maxima: Assign value to a variable, by addressing it in a matrix -4.05
Replace the text in sed 0.00
Verilog continuous assignment equivalent of always block 0.00