| Title |
Δ |
| How do weak ISAs resolve WAW memory hazards using the store buffer?
|
0.00 |
| MIPS Load Word Placing
|
0.00 |
| What is the nasm assembly code version of gcc inline assembly
|
-1.61 |
| Memory capacity saturation and minor page faults
|
0.00 |
| Assembly Visualizer
|
0.00 |
| Possible to write various-typed value to a memory address with a si...
|
-1.28 |
| How to execute "invd" instruction?
|
0.00 |
| What are the key differences between general-purpose processors and...
|
0.00 |
| How is FASM a low level assembler and NASM a high level assembler?
|
0.00 |
| x86_64 efficiently set bit N in register DST if N < width(DST),...
|
-0.56 |
| What is the relation to the order of which memory is stored
|
0.00 |
| How to initialize an array of 16-bit integers in ARM64?
|
-1.70 |
| TASM code gives error in YASM: instruction expected after label
|
0.00 |
| How to auto-vectorise a loop which 1) modifies an array, 2) indicat...
|
0.00 |
| MIPS-32 Opcode Format: Uppercase or Lowercase?
|
0.00 |
| Keep only the 10 useful bits in 16-bit words
|
-2.58 |
| How to best emulate the logical meaning of _mm_slli_si128 (128-bit...
|
-1.94 |
| SIMD search for trough after the last peak
|
-2.36 |
| Analogy between 2 CPU having same Instruction Set Architecture (ISA)
|
0.00 |
| Why do alignment restrictions change the behaviour of clang while v...
|
+1.79 |
| Is "jr $ra" required to end a MIPS assembly language prog...
|
+1.60 |
| Is it good or bad (performance-wise) to use std::vector<Vec8d>
|
+0.13 |
| How is a tword ten bytes instead of 20?
|
0.00 |
| How many clock cycles do the stages of a simple 5 stage processor t...
|
0.00 |
| memory_order_relaxed and visibility
|
-1.22 |
| Why does x86 paging have no concept of privilege rings?
|
+0.98 |
| Execute in memory binary with c
|
+0.38 |
| lscpu and cpuid say I have AVX2, but vpsllvw does not work
|
0.00 |
| AVR Assembler check is number odd
|
+1.33 |
| Conditional move (cmov) for AVX vector registers based on scalar in...
|
+0.43 |
| How do labels execute in Assembly?
|
-2.69 |
| Negative decimal to fixed-point binary
|
0.00 |
| x86-64 assembly online, with an IDE such as https://www.mycompiler....
|
0.00 |
| Does the position of a function/method in a program matters in case...
|
0.00 |
| Does RDTSCP increment monotonically across multi-cores?
|
0.00 |
| What does [--][--] mean in the Intel x86 Assembly docs?
|
0.00 |
| Why does `add cx, 1234` in NASM 16 bit mode produce <unknown>...
|
0.00 |
| Is the accessing speed of the RAM/Disk Memory dependent on its volu...
|
0.00 |
| Inconsistent `perf annotate` memory load/store time reporting
|
0.00 |
| Which are the use case of punpcklbw (interleave in MMX/SSE/AVX)?
|
0.00 |
| Why is struct of arrays not vastly faster than array of structs in...
|
0.00 |
| Why make some registers caller-saved and others callee-saved? Why n...
|
0.00 |
| single-reader single-writer fix-sized ringbuf, without lock and ato...
|
0.00 |
| Assembly Compilation failed dued to unrecognized character
|
-1.81 |
| shared_lock implemented with std::atomic
|
0.00 |
| TAGE prediction accuracy improves with loop over larger array?
|
0.00 |
| Why does some Windows booloader code zero registers with `sub` inst...
|
+2.04 |
| How to unset N right-most set bits
|
0.00 |
| Can I compile Go programs on Xeon Phi (Knight's Landing) proces...
|
+1.18 |
| Can code built with g++ -march=x86-64 run on a 32-bit Operating Sys...
|
0.00 |