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Rating Stats for

Peter Cordes

Rating
1575.42 (3,453rd)

Reputation
156,434 (349th)

Page: 1 ... 7 8 9 10 11 ... 92

Title	Δ
Instructions to copy the low byte from an int to a char: Simpler to...	0.00
why we can't move a 64-bit immediate value to memory?	0.00
Can x86-64 return instruction cause a page fault in linux? Is the c...	0.00
Lockfree buffer updates with variable-length messages in C	+1.64
(asm x86) Is there an instruction similar to add, but involving a r...	0.00
What is the correct calling convention to use within a bootloader?	+0.37
Computer dedicated to one program	-0.79
Matrix Multiplication using SIMD vectors in C++	0.00
Calculate memory accesses	0.00
load 32 bit immediate value in RISCV memory	0.00
MIPS pipeline with beq following a lw instruction?	0.00
Why isn't there a clear SREG RISC instruction?	+0.38
What is the most direct way of addressing a graphics chip?	+0.35
Why is my C++ program's assembly output full of .ascii with no...	0.00
Get the register causing a segmentation fault in a signal handler	0.00
gdb - how to disassemble whole function including loops	+0.04
Am I guaranteed to not encounter non-64-bit instructions if there a...	0.00
explanation for the illegal instruction when eax is zero	0.00
Does single core speed benefit from a huge L3 cache?	0.00
Is there a function to load a non-atomic value atomically?	0.00
How to use conditional assembly to remove this redundancy using MASM?	0.00
stack space for a vector that its size is given at runtime? (C code)	0.00
What happens for a RIP-relative load next to the current instructio...	0.00
Programming Language Fundamental Instructions Unit?	+1.20
How are void pointers implemented?	-0.84
Is this assembly code sorting numbers in ascending order?	0.00
Reducing bus traffic for cache line invalidation	0.00
ARM and x86, is necessary deal with Hardware Architecture compatibi...	-0.74
Find the end of a list in Assembly	0.00
With AVX/AVX2/SSE __m128i set all bytes that are negative to -128 (...	-1.69
How are relocations supposed to work in static PIE binaries?	+2.06
Where is the Linear Address Space located?	0.00
AVR assembly - bit number to mask	-0.92
Data hazards in hardware platforms	0.00
How to force compiler to generate conditional move by using inline...	0.00
Where I should use "swapgs" instruction	+1.66
Are these the smallest possible x86 macros for these stack operatio...	0.00
error: unsupported size for integer register	0.00
Why do compilers construct a graph in register allocation?	+0.84
Does dirty bit (of TLB) need to be setted always on a store?	0.00
Are there compatibility issues with clang-cl and arch:avx2?	0.00
Could branch prediction optimization be inherited?	-2.02
In "latency value table": latency values of each level ca...	0.00
Is movzbl followed by testl faster than testb?	0.00
java code to calculate running time for sorting algorithms	0.00
atomic linked-list LIFO in AArch64 assembly, using load or store be...	0.00
How does Intel X86 implements total order over stores	0.00
Relative Benchmarking in R adjusted for Local Machine Specs	0.00
How Reordering instruction solve the data dependency?	0.00
Why do we use sub esp, 4 instead of push a register in assembly?	0.00