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Rating Stats for

Peter Cordes

Rating
1575.42 (3,453rd)

Reputation
156,434 (349th)

Page: 1 ... 9 10 11 12 13 ... 92

Title	Δ
How to compile a linux kernel with SSE enabled?	0.00
What cache coherence solution do modern x86 CPUs use?	0.00
What is the point of SSE2 instructions such as orpd?	0.00
Why is ONE basic arithmetic operation in for loop body executed SLO...	+0.91
Memory barriers on entry and exit of Java synchronized block	+1.39
x86 how does Linux signal interrupt instruction stream	0.00
Lock-free SPSC queue implementation on ARM	0.00
Is generating random numbers from hardware performance cryptographi...	-2.81
How can I delay a loop iteration accurately to hit frequencies like...	0.00
lubuntu does not see executable file generated by ocamlopt on NixOS	0.00
Partial-compare-and-full-swap for atomic values	+0.22
Is this a proper way to extract a byte from a NEON uint8x16_t vector?	0.00
Reading registers in the GCC using a char pointer	0.00
How can I effectively time the execution of a function that's o...	-0.23
assembly, how to use mprotect?	0.00
Assembly: Occurrence of Integers in Array	+0.35
Why bubble sort is not efficient?	+0.37
Should the assembler not honor my request for ret imm16?	0.00
atomic_ref when external underlying type is not aligned as requested	0.00
C++11: are 16-byte atomic<> variables automatically aligned o...	0.00
Don't understand why MIPS assembly questions are incorrect	0.00
Avoid unnecessary mov ecx, ecx instruction in bzhi(y, tzcnt(x))	+0.38
find nan in array of doubles using simd	0.00
Trouble returning float value from fpatan assembler function back i...	0.00
Is it possible to get the native CPU size of an integer in Rust?	0.00
clang __asm__ with labels in case statment, gets error: invalid ope...	0.00
unlimited precision NASM calculator using linked lists	0.00
Who decides which instructions are to be kept privileged? Is it the...	0.00
Loop fission/invariant optimization not performed, why?	0.00
what happened if store with memory_order_acquire	0.00
C++11 atomic<>: only to be read/written with provided methods?	0.00
Using the blend instructions in intel intrinsics (AVX)	0.00
Intel PIN: How do I see speculative instructions?	+2.00
Using square brackets in x86	0.00
what does extra symbol and assembly code mean?	0.00
Population count in AVX512	0.00
Does each core have its own mask (k0-k7) registers?	0.00
SIMD instructions on contiguous iterators	0.00
Is L2 line fill always triggered on lookup?	0.00
Sum of linked list values in assembly x86	0.00
How can one figure out if a loop is being entered with a 16 byte al...	0.00
Allocate writable memory in the .text section	0.00
Observing x86 register dependencies	0.00
Assembly sscanf	0.00
Why is there barrier() in KCOV code in Linux kernel?	0.00
Using XSETBV to write to XCR0 creates a general protection fault in...	-0.60
Checking possible Hazards from Assembly Code	0.00
Why is does MIPS use 'PC+4' as base address when calculatin...	0.00
Is Little Man Computer still relevant?	-0.37
Why any modern x86 masks shift count to the 5 low bits in CL	-0.25