StackRating

An Elo-based rating system for Stack Overflow

Home | About | Stats and Analysis | Get a Badge

Rating Stats for

Morten Zilmer

Rating
1580.34 (2,977th)

Reputation
12,768 (11,398th)

Page: 1 2 3 4 ... 9

Title	Δ
Unsigned in VHDL	0.00
vhdl 32bit counter on 16bit bus	-1.80
MIPS overflow exception	0.00
VHDL extract constant from entity	+2.08
VHDL bidirectional bus mismatch	0.00
verilog code in Ise	-0.12
<> of the instance <gen[1].> is unconnected or connec...	0.00
How to infer variable name in a for-generate block?	0.00
Use a type before it's declared in VHDL (2008)	-1.65
Infer 2d block RAM in VHDL for Xilinx vivado	-0.07
How to select specific PLL?	0.00
Case statement vs If else in VHDL	+0.38
How to see content of look up table	+0.39
Clock Management Altera DE 1	0.00
Modelsim - too many iterations in simulation (verilog)	0.00
is there any possibility for "if" block to go out of give...	0.00
Read textfile in VHDL testbench	0.00
How to do a vector product in VHDL	0.00
error when elaborating in design vision	0.00
VHDL when-else error	0.00
in vhdl case statements,how to deal with 4 value logic?	+1.70
Generic vector in VHDL, with position of assignment determined by v...	0.00
VHDL simulation error: "delta count overflow"	0.00
should signals in vhdl be signed/unsigned to perform arithmetic ope...	-0.54
Constant value of ROM array	0.00
How to modify the Verilog code to avoid multiple drivers?	-0.85
conversion from unsigned to integer in vhdl	0.00
Using a variable in more than one funciton?	-0.62
Signal x cannot be synthesized, bad synchrononous description	+1.71
VHDL can't determine definition of operator "+"	+0.39
How to add altera lib for simulation with ModelSim?	+0.39
Expected a more extensive RTL Viewer	0.00
How to delete trailing whitespace in Verilog Mode Emacs	0.00
Index overflow in VHDL std_logic_vector	0.00
near text "=" expecting "(" or " ' &qu...	0.00
VHDL parse error, unexpected DIV	0.00
For loop goes into infinite loop when I use a variable as ending co...	0.00
Variable or Signal Needed?	0.00
Output get initialized with U logic in simulation in vhdl	+1.68
Verilog 5 ways of defining the same logic, Is there any difference...	0.00
Serializing code in VHDL	0.00
How to deal whith VHDL generics in code coverage	0.00
How to split the sequential and the combinational in verilog	+0.40
How to initialize a wire with constant in verilog ?	0.00
How to solve the error "signal has multiple source"?	-0.09
Optional PORTs in VHDL?	0.00
VHDL constant in generics	+0.41
Unexpected behavior of simple VHDL circuit	0.00
Verilog Making a divide by two counter out of D Flip Flops not work...	0.00
How to get the first 3 values of an array using VHDL?	0.00