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Rating Stats for

Morten Zilmer

Rating
1580.34 (2,977th)

Reputation
12,768 (11,398th)

Page: 1 2 3 4 5 ... 9

Title	Δ
VHDL syn_looplimit and synthesis	+0.40
VHDL : Signal s Cannot be Synthesised	-2.32
How to use Quartus to optimize combinational logic?	0.00
Avoid using inout in VHDL	+0.91
Mapping Error related to trimming of signals	0.00
compiling fphdl in Altera Quartus Prime	+1.72
vhdl program not swapping integers	+0.43
VHDL - Do I have to use the same clock signal in every sequential p...	0.00
How to/Can you use if statement to an Assert Report Severity Statem...	0.00
How good are VHDL's random numbers?	0.00
How to stop a simulation by timeout?	+0.67
VHDL - direct instantiation for PLL	0.00
FPGA implement memory mapped register	0.00
Possible to create a dictionary type data structure in VHDL?	0.00
How to convert array of std_logic_vector to integer in VHDL	0.00
How is /= translated to actual hardware in vhdl	+1.46
declaration of an std_logic_vector having a variable size in VHDL	+0.40
VHDL assignment when ... else renders syntax error	0.00
VHDL behavioural D Flip-Flop with R & S	-0.08
Generic MUX and DEMUX using Generics	0.00
Where should I call an initializer function of a protected type in...	0.00
What I'm missing in this simulation?	0.00
How can I build if sentence with compare to various values?	0.00
How to increment std_logic_vector within an array type using index?...	-1.42
How to use vsim.exe (asim) in Aldec Active-HDL Student Edition?	0.00
Alternative method for creating low clock frequencies in VHDL	+0.44
Are muxes more "expensive" than other logic?	+1.76
How can I generate a "tick" inside a process in VHDL?	0.00
I'm getting an error while using sll	0.00
VHDL inferring latches	+0.44
Gated Clock in Clock Divider for a Square Wave	-0.57
Signal temp2 cannot be synthesized, bad synchronous description	+0.40
Synchronous vs Asynchronous Resets in FPGA system	+0.40
std_logic to integer conversion	+0.40
vhdl subtract std_logic_vector	0.00
Case statement error message in VHDL	-0.07
VHDL 8-bit multiplier, 3-bit input and 4-bit input, how to compensa...	+1.76
How to map a single bit of a signal to multiple bits of a Vector?	0.00
Trying to understand simulation errors with Xilinx	0.00
Passing clock between entities	+0.41
Actual expression for generic slaves cannot reference a signal	0.00
it does not hold its value outside the clock edge	-0.24
In VHDL is there a difference between declaring one large vector an...	0.00
VHDL - "Input is never used warning"	0.00
Delay in VHDL process between adjacent statements	0.00
Generating post-synthesis verilog model in Quartus II	0.00
Structural Architucture Simulation in ACtive-HDL	0.00
Why does this code work only partially?	-0.94
VHDL How to assign outputs from file as constants in package?	0.00
Prepending by element or array in addition	0.00