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Rating Stats for

Jim Lewis

Rating
1540.49 (11,572nd)

Reputation
2,359 (71,486th)

Page: 1 2 3

Title	Δ
Process or not to Process?	+3.94
What's the right way to cast a sfixed to std_logic_vector in vh...	+0.87
Recursive 'type' declaration in VHDL	-4.27
VHDL: button debounce inside a Mealy State Machine	-4.13
Test bench RS232 Protocol VHDL	0.00
VHDL unnecessary value after (to_unsigned) conversion	0.00
In VHDL is there a way of limiting the size of a string with a vari...	+3.64
How to return a blank line in ISim?	0.00
How to display a sentence with VHDL on a FPGA board	0.00
VHDL textio, reading image from file	-2.26
VHDL: Why is 'length not defined for enums?	+3.83
Passing the (initial) value of a shared variable to a generic durin...	-3.82
rising_edge(clk) not synthesizable	+4.16
Vhdl-Code testbench why are there no ports declared	+3.94
padding out std_logic_vector with leading zeros	-0.30
VHDL simulation failed with unexpected result	0.00
VHDL Assigning Multiple Values to One Signal	0.00
Compare std_logic_vector to a constant using std_logic_vector packa...	+4.04
VHDL adding 2 std_ulogic_vector does not have any effect	0.00
Top level using port maps with records in VHDL	0.00
Creating large dual-port RAM in VHDL	0.00
Why am I getting a "No matching subprogram was found." er...	+4.19
VHDL pulse generator on the press of a button	0.00
Subtractor Module VHDL generating wrong values	-2.16
How to get simulation warning when comparing std_logic with 'X&...	-0.10
My function does not return a value, and I do not understand why? V...	-2.20
How can I extract elements from a record using an integer reference...	+4.31
Get internal signals of vhdl design in ncvhdl (alternative to model...	+3.88
Illegal type conversion VHDL	+3.97
VHDL Testbench code doesn't work for register	+3.48
Record fields assigned from different processes	0.00
VHDL state transitions based on if statements - works on board but...	+0.05
vhdl comparing vector output	-2.08
Parse error, unexpected STRING_LITERAL, expecting PIPE or ROW VHDL	+3.88
Few questions on microprogrammed control (VHDL)	0.00
Can I make a nested with-select-when statement in VHDL?	-4.22
Pattern generation using Vhdl...?	0.00
Pattern generation using Vhdl...?	0.00
compiler errors when compiling *.vhdl into a library - Altera Quart...	0.00
compiler errors when compiling *.vhdl into a library - Altera Quart...	0.00
Using the VHDL 2008 generic type feature to create pseudo-dynamic t...	-2.72
VHDL test bench error please help, for school (SOLVED)	-3.40
How to use conditional assignment when portmapping	-0.22
Small change in VHDL register file results in huge difference in to...	0.00
Latch generated when attempting to create a memory bus in VHDL	-0.10
VHDL Code Help -Break integer into pieces	+4.27
VHDL: std_logic_vector Leftshift and right shift operator?	+3.93
VHDL compiler error	+4.14
Unsupported feature error	0.00
How to simulate memory on VHDL test bench?	0.00