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Rating Stats for

Jim Lewis

Rating
1540.49 (11,572nd)

Reputation
2,359 (71,486th)

Page: 1 2 3

Title	Δ
Unintentional latches in finite state machine (VHDL) + feedback	-2.54
Wait until <signal>=1 never true in VHDL simulation	+0.12
How to manage large VHDL testbenches	+4.22
what is the difference between synthesis and simulation (VHDL)	-4.19
AND all elements of an n-bit array in VHDL	-2.55
issue related to loading modelsim simulation	0.00
found '2' definitions of operator "=" in VHDL program for...	+3.97
Changing IF statements, saving some code	+4.04
Binding systemverilog cover group with vhdl module	0.00
VHDL Design - Clock	-1.52
How to output array elements in random order using VHDL	+2.70
VHDL assignment slice not implemented?	+4.06
test bench multiple architectures	+4.10
Cases throwing unexpected when	-3.56
VHDL Bus Functional Modelling - Can't put groups of procedures into...	+0.43
Make a signal wait until falling edge	-1.69
Using FOR loop in VHDL with a variable	+4.02
Getting Modelsim simulation time instant as a string variable?	-3.56
VHDL equal operator: different behavior for std_logic and std_ulogic	+2.05
Convert real to IEEE double-precision std_logic_vector(63 downto 0)	+4.65
Flip flop implementation with process. [VHDL]	-3.83
16 bit 2's complement adder in VHDL	0.00
Project on MIPS pipelined processor	-4.01
VHDL - Conditionnal attribute declaration depending on a generic	+1.86
How to compare integers in VHDL? What is my mistake?	+2.33
VHDL, confused over syntax "" &	-3.91
Generate random values in VHDL function	-3.89
Error testing 8-bit LFSR written in VHDL	0.00
Developing multi-use VHDL modules	0.00
Active-HDL simulation clock crossing	0.00