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Rating Stats for

Jack Koenig

Rating
1503.96 (251,869th)

Reputation
2,673 (63,199th)

Page: 1 2 3

Title	Δ
What mechanism works to show component ID in chisel3 elaboration	+0.33
For loop representation in Chisel (@Normalization in Float Adder)	-3.76
java.lang.AssertionError: assertion failed:	0.00
Type Class for Complex Numbers	+3.74
Conditional Bulk Connection <>	0.00
How to replace combinational memory with ASIC cell in Chisel	0.00
Any way to work around JVM code size limits tripped by large Chisel...	+4.05
How to generate Verilog code with parametized modules in Chisel?	0.00
How to make assertions in Chisel be just warnings and not stop simu...	-3.79
Assigning values to the elements of a bundle by parsing a file	0.00
chisel "Enum(UInt(), 5)" failed	+4.94
assigning a signal to a non parent module	0.00
Implement a Verilog $onehot task in Chisel	0.00
How to init a register with a parametrized value	0.00
Chisel3 compare UInt bits every clock cycle [runlength encoder]	0.00
Chisel: Decoupled directionality lost in nested Vecs	0.00
Advanced Parameterization Manual in Chisel	+0.18
Rebased and now facing Scala dependency issues	0.00
Pass strings in Chisel	0.00
Sink and Source are different length Vecs	0.00
test rocket chip util 'Arbiters.scala', got error 'bits...	0.00
Bit width inference issue	0.00
Required: T Chisel Error	0.00
How to convert Vec(n,Bool()) into UInt value	0.00
Implement high impedance 'Z' input output property with chi...	0.00
How to Paramatrized vector of registers in chisel	+0.14
How to perform gate level simulation in Chisel3?	0.00
What is the difference between class(val a: Int) and class(a: Int)?	-4.33
Scala Traits - how to implement method	-4.28
How to specify chisel’s post-processor?	+3.88
Chisel/Firrtl Verilog backend proof of work	0.00
How to add additional IO under certain condition to RoCCIO in Chisel	-4.09
How to change timescale in vcd generated by chisel3 iotester	0.00
How to partially initialize a vector of registers (e.g. some fields...	0.00
Converting Chisel to Vhdl and SystemC?	0.00
How to connect Bits to SInt in Chisel	0.00
Chisel, Generate Blocks and Large Intermediate/Output Files	0.00
How to cast UInt to SInt value in Chisel3?	0.00
where is the root directory of setResource in chisel3?	0.00
How to add verilog synthesis directives in Chisel3?	0.00
Chisel/FIRRTL constant propagation & optimization across hierar...	0.00
sorting a List of integers pairs such that List[(Int,Int)] in scala	0.00
Chisel code translating into Verilog/C++	-0.08
How to traversal or return the signalName of all elements of a bund...	0.00
Chisel3: False Combinational Loop in Fixed Priority Arbiter	0.00
Chisel3 disable GEN wires	0.00
Can chisel print macros into the RTL	0.00
port name issue of those are defined in the BlackBox	0.00
can chisel translates firrtl to verilog in parallel/multi cpu?	+3.83
chisel function on the left side of the assignment	0.00