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Rating Stats for

Jack Koenig

Rating
1503.96 (251,869th)

Reputation
2,673 (63,199th)

Page: 1 2 3

Title	Δ
why chisel UInt(32.W) can not take a unsigned number which bit[32]...	-4.17
Chisel code transformation	+3.87
Chisel UInt negative value error	0.00
Disable FIRRTL pass that checks for combinational loops	0.00
Power operator in Chisel	0.00
Scopes in Chisel and scala	0.00
top level naming in chisel3	0.00
Initialize data in Mem (Chisel)	0.00
Generating Chisel Module IO Interface From a List	0.00
In chisel, how to define a common ZERO for all Data type?	0.00
How to create a Vecs of register by Chisel	0.00
How to specify squaring the difference of two unsigned numbers in C...	-0.08
Not bound to synthesizable node exception and type mismatch error i...	0.00
How to initialize the data of a Mem in Chisel3	-4.17
Not bound to synthesizable node exception in chisel memory	0.00
Simplest way to generate Verilog code from Chisel code	0.00
Initialize class depending on config value	0.00
Chisel memory write mask	0.00
Dynamic test harness in chisel 3	0.00
How to make Chisel generate flip flops with enable?	-0.18
How to trace an uninitialized signal in Chisel?	0.00
How to initialize ShiftRegister primitive in Chisel	0.00
Usage of clone method in Chisel IO interface constructors	0.00
How to delete clock signal on chisel3 top module?	0.00
How to instanciate Xilinx differential clock buffer with chisel3 bl...	0.00
Chisel language how to best use Queues?	0.00
Chisel library and testbenches	0.00
Incorrect syntax of Chisel	0.00
Chisel testing error in sodor/ rocket core ALU	0.00
Chisel not finding the implicit value of a parameter	0.00
Chisel: mapping separate input and output ports to inout pin	0.00
Chisel 3 assignment to bit range	0.00
Reassign a variable multiple times within a clock cycle - Chisel	0.00
Error after running "sbt test" in Chisel 3	0.00
Compiling chisel source files in chisel project template	0.00
Syntax about chisel :Vec & Wire	+4.02
Use generic type to turn off logic in datapath (Chisel)	+3.87
Chisel3. Functional Module Mux4	+3.96
What does '&' and '%' mean in operators -&,...	0.00
Is there a simple example of how to generate verilog from Chisel3 m...	0.00
Passing an array into Perl subroutine	+3.70