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dave_59

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1560.31 (5,540th) 		Reputation
21,379 (6,248th)
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How to drive multiple object types onto a net in AMS? 0.00
Declaring an array of enumerated types 0.00
Systemverilog localparam array with configurable size 0.00
`uvm_do_with with inline constraints 0.00
Best way to describe in Verilog +0.40
Quote macro literal string argument inside string 0.00
Verilog: Is there a way to make a generalized adder (variable width... 0.00
Macros in package 0.00
How to check SV class property existance 0.00
Debug help : enum reg is incompatible with reg port +1.94
wrong values at adder output in verilog module 0.00
How to change input signal to parameter in systemverilog? +1.96
While loop with non-constant loop conditions, but using parameter +1.99
get virtual interface once in package -0.26
Value in register keeps resetting to 0 every clock cycle -0.59
Dynamic array of interfaces in SV 0.00
How to generate ctags for system verilog? -0.07
Would there be an issue, for system verilog functional coverage bin... 0.00
Output is Always X 0.00
How do I dynamically instantiate hardware from a list of available... 0.00
General type input of function -0.59
Synthesize-able delay in Verilog -0.07
How to create random dynamic 2D arrays in SystemVerilog? 0.00
How to declare input/output ports dynamically (show/no show) in ver... +0.37
Driving a internal wire in my module from my interface task +0.34
Can't implicitly connect port on instance error -0.60
When are (System)Verilog parameters calculated? 0.00
verilog, i have to define 31 "and" gates , it is showing... 0.00
Inertial Delay in System Verilog 0.00
SystemVerilog - How to find the max value in queue? 0.00
system verilog always within always +0.47
Verilog error: Range must be bounded by constant expressions 0.00
Systemverilog rule 4.7 (nondeterminism) is interpreted differently... 0.00
system verilog disabling `ifndef blocks in specific instances -0.82
Undeclared port verilog error 0.00
In systemverilog is there a way to condition on a type? +1.99
Scope of `define macros +0.40
Interface cell not supported system verilog 0.00
How to calculate propagation delay of a combinational circuit? 0.00
Assign string variable to array using for loop +0.90
Is event trigger synthesizable in verilog? +0.41
how to alias signals from a nested interface in system verilog? 0.00
Do Compilers for FPGA Languages Perform Optimizations? +0.40
compile and simulate an UVM TB in Modelsim 10.4b 0.00
Order in always_comb block 0.00
How to get fork join/join_any to work with a loop +2.02
Using an array of parameters to generate modules 0.00
Verilog. Multidimensional array initialization 0.00
Port size error in Verilog 0.00
SystemVerilog Variable index in generate block items 0.00