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Rating Stats for

Chick Markley

Rating
1553.05 (7,102nd)

Reputation
1,560 (105,281st)

Page: 1 2 3

Title	Δ
Vec of Bundle as a Module parameter	-4.67
Examples in Chisel that make use of MuxCase	0.00
"for-loop" to reduce coding on Chisel3.2	-4.46
How to fix chisel test errors whit Verilator (should work with veri...	0.00
Chisel : When-otherwise clause not working in function definition	-0.73
Looping through a circular buffer in Chisel	0.00
firrtl_interpreter.InterpreterException: error: ConcreteSInt(303, 9...	0.00
RisingEdge example doesn't work for module input signal in Chis...	+3.33
how to pack zeros in to bundles in chisel	0.00
How can i blackbox code for a part in chisel?	0.00
Add registers of sub-module to the regmap() of a module that new/in...	0.00
Using Multiple Clocks in Testers	+3.50
How to writing a accumulator by using ScalaBlackBox?	0.00
Why multiple HCL languages	0.00
How to use a chisel3.experimental.ChiselEnum in an I/O port?	+3.68
How do you instanciate a same module twice?	0.00
How to generate an [error] instead of an [info] upon seeing a wrong...	0.00
Chisel3: How to create a register without reset signal in RawModule?	0.00
What mechanism works to show component ID in chisel3 elaboration	-0.33
For loop representation in Chisel (@Normalization in Float Adder)	+3.76
Chisel how to test only one package	+3.63
Not sign-extended in AND operation in firrtl	0.00
Why does implicit type conversion from Int to UInt not work?	0.00
How to get the PeekPokeTester expect function to print signal value...	0.00
Compiling Modules Separately and Linking	0.00
How to iterate through similar registers definition in Chisel (regm...	0.00
Testing a DSPComplex ROM	0.00
Building a DspComplex ROM in Chisel	0.00
Chisel testbenches: controlling multiple ports independently	0.00
How to printf or println UInt in chisel?	-0.41
How to make assertions in Chisel be just warnings and not stop simu...	+3.79
The type mismatch error while using Chisel3 BlackBox	+3.66
How to use chisel dsptools with floats	+3.71
Multiple clocks support in chisel iotesters	0.00
Advanced Parameterization Manual in Chisel	-0.18
BlackBox feature in chisel3	+3.79
How to avoid multiple design elaborations in Chisel testers	0.00
Break statement in Chisel	0.00
Wiring Seq of chisel modules	0.00
How to Paramatrized vector of registers in chisel	-0.14
How to add each element of Vec?	0.00
Mem read and write at same index and in same cycle	0.00
Test Multiple Instance in a single PeekPoker Test	0.00
Error infor: bits operated on 'chisel3.core.Bool@32' must b...	0.00
Doubts about Chisel dontTouch API and FIRRTL optimiztion	0.00
Unconnected wires doubts	0.00
Reset Logic in Chisel	0.00
Chisel memories support read masks directly?	0.00
Chisel3 based Hardware Accelerator for Risc-V Rocket generator?	0.00
Chisel2 code run invoking compatibility layer - type casting issues	0.00