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scary_jeff

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1566.79 (4,475th)

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3,744 (44,863rd)

Page: 1 2 3

Title	Δ
Vhdl code simulation	+3.98
BCD to bargraph decoder vhdl design code	-0.30
ERROR:HDLCompiler:806 3 syntax errors that in parts are ignored why?	0.00
Compile error with operator ""&""" vhdl	0.00
Using Custom Packages Causes Circular Dependency	-4.29
VHDL: button debounce inside a Mealy State Machine	+4.13
Variable number of inputs and outputs in VHDL	0.00
HDLCompiler:432 error on converting std_logic_vector to integer	0.00
VHDL <b_Off_OBUF> is incomplete. The signal is not driven by...	0.00
New DCM CLK instantiation error?	-4.64
Cannot create latch and counter with 2 clock signals in VHDL	0.00
Wrong Truth Table for 2 bit comparator using 2 inputs and 3 outputs	0.00
Reporting std_logic_vector as an unsigned integer in ISim?	0.00
Converting std_logic to integer within testbench?	0.00
How to display the amount of errors that occured in a self-verifyin...	-0.48
generate statement with dsp48	0.00
Input Signal Edge Detection on FPGA	0.00
Error for if statement condition in adder/subtractor	+4.61
Sum dynamic amount of vectors	+4.17
VHDL Pulse Generator Seems Stuck	0.00
Array of 1-bit-wide memory	+3.54
4 bit magnitude comparator VHDL	0.00
VHDL average of Array through for loop	0.00
Multiple behaviours for single entity	+4.66
Object is used but not declared?	0.00
FPGA logic cells	+3.85
Signal current cannot be synthesized, bad synchronous description	0.00
Square Waveform Generation in VHDL	0.00
How to execute 'Zoom Fit' in ModelSim/QuestaSim from TCL co...	0.00
VHDL clock generator with different speeds using button	0.00
Pull down a pin output at the same time set as Z state VHDL	0.00
initializing memory in VHDL	0.00
VHDL:clock divider	0.00
Error(10820) and (10822) VHDL	-0.09
How to design a decoder that will have extra outputs?	0.00
Tips and tricks for vhdl design debugging	+3.95
How would one go about implementing an add immediate in Verilog for...	0.00
Dynamic signal creation in VHDL and solution of VHDL error: Syntax...	0.00
LSFR counter for random number	-0.03
1 bit ALU whose operations depend on carry in	0.00
VHDL Finite State Machine - Is the reset really necessary?	+2.17
Using .do files with ModelSim (10.3a)	+3.98
VHDL code to convert 5 bit vector to integer	0.00
Syntax errors in VHDL - in case statements	-1.93