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Rating Stats for

Marty

Rating
1548.81 (8,295th)

Reputation
5,171 (32,031st)

Page: 1 2

Title	Δ
Vector as parameter in #()	0.00
Verilog - range handling with named values	0.00
Does $fopen function in Verilog support user argument?	0.00
Any benefits from implementing CSA versus just using multiplication...	+3.52
always block @(*) means?	+3.52
Block is unconnected and will be trimed Verilog	-4.53
random number generator on Zedboard (Xilinx Zynq-7020)	-0.54
Arithmetic shift acts as a logical shift, regardless of the signed...	0.00
Way to initialize synthesizable 2D array with constant values in Ve...	0.00
Error (10170): Verilog HDL syntax error at alarm_clock.v(133) near...	0.00
IO File Read/Write Verilog	0.00
Verilog: Reg is not declared	0.00
Low Latency FWFT Fifo in Verilog	0.00
Verilog + FPGA: If statement for switch	0.00
Turning a number negative in Verilog	0.00
store the output of shift register in RAM in verilog	0.00
Multiplying number by ten in verilog	+3.58
6bit ORgate Verilog	0.00
What is a good book for functional verification digital IC design?	+0.96
Is there a more concise way to write the assign for this wire in Ve...	0.00
led pattern finite state machine verilog	0.00
How to set registers of an external ADC	+0.37
Verilog : Simple I2C read operation	0.00
Arduino: Is the command Serial.print("some string text")...	+3.48
What is the best way to store strings on an Arduino?	0.00
Why is my D Flip Flop not waiting for the positive edge of the clock?	0.00
How to initialize an array of integers?	0.00
Verilog : Module parameter, code simulates but doesn't synthesize	0.00
Debugging combinational logic loops in Icarus Verilog	-2.22
Non-void function used in void context?	0.00
Incrementing Multiple Genvars in Verilog Generate Statement	0.00
Difference between @(posedge Clk); a<= 1'b1; and @(posedge Clk)...	0.00
Could we have generate inside an always block?	0.00
How do languages related to FPGAs?	-4.49
Preventing latches within Verilog case statement	0.00
combinatorial hardware multiplication in verilog	+3.43
Accessing Verilog genvar generated instances in simulation code	+0.04
Synthesis error in Verilog	+3.39
Specifying variable range in verilog using for loop	0.00
Passing arrays to verilog modules	0.00
Systemverilog problem with always_comb construct	+1.70
How to use const in verilog	0.00
verilog assignment compiler error	0.00
converting a wire value to an integer in verilog	0.00
? time delay, when using === or <=	-0.15
not a valid l-value - verilog compiler error	0.00
Verilog: is it possible to do indexed instantiation?	+3.89
Specifying signal delays in SystemC as clause AFTER in VHDL	+2.98
Understanding types in SystemC	+3.70
How to run a pattern without using delay()	0.00