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Rating Stats for

Philippe

Rating
1529.86 (18,638th)

Reputation
3,104 (54,462nd)

Page: 1 2

Title	Δ
Syntax error in if statement in vhdl	+3.67
Whats the meaning of "for(;;)"	-2.85
CPU.hdl - Need explanation to understand the code	0.00
Finite State Machine in vhdl	0.00
Using functions in VHDL for synthesis	-2.25
Generated random number VHDL	-0.12
My VHDL ALU code behave awkward	-4.50
using when...else statment in port map	+3.63
Implement equation in VHDL	-1.81
vhdl error 827: signal <> cannot be synthesized	+3.66
Compare std_logic_vector to a constant using std_logic_vector packa...	-0.99
VHDL - ModelSim testbench simulation freezes when sending "run...	-0.47
Comparing reals in VHDL	-4.25
vhd xlinix something is wrong same values it must be with muxes	+3.76
I've this error :Error (10344): VHDL expression error at REG2.v...	-0.24
VHDL ERROR: unexpected IDENTIFIER	0.00
VHDL - unconnected components in top module	-0.38
FPGA synthesizable verilog code with floating point numbers	-0.52
Lightweight VHDL simulator in Windows	-2.83
VHDL Process Confusion with Sensitivity Lists	0.00
VHDL Code for Binary Division bug	0.00
Inferred RAM doesn't initialize in ModelSim Altera edition	-0.42
VHDL Array element in if-statement	+3.76
error: expression ""00000000000000000000000000000000"...	0.00
Array of arrays not simulating	-0.28
VHDL invert if to reduce nesting	-1.36
VHDL MUX select with constant	+3.64
Unintentional latches in finite state machine (VHDL) + feedback	-2.92
Generate Keyword in VHDL	-4.47
VHDL signal assignment leads to uninitialized state	+0.30
VHDL Pullup Resisters	-0.62
Signal not changing state in iSim	-0.62
How copy or save Lint warnings in Eclipse	-4.72
How to convert 8 bits to 16 bits in VHDL?	+1.58
VHDL Value in case statement randomly gets stuck at a certain value	-0.49
How to compare integers in VHDL? What is my mistake?	+1.48
Check every element of array of record is 0 in VHDL	-2.50
SystemC how to get interactive user input	0.00
VHDL Syntax explanation needed	+3.50
Can somebody help for 5x7 dot matrix display simple VHDL code for c...	-0.51
VHDL tags not efficient in vim with ctags+taglist	-4.52
Using records in type generics	0.00
How to connect components of VHDL code	0.00
FSM machine in VHDL with each state DOING CERTAIN OPERATIONS	0.00
VHDL shift operators?	-0.66
VHDL code does not synthesize	-0.56
Problems opening files from a VHDL process into an entity instantia...	-0.14
How to suppress "unused variable" warnings in Eclipse/PyDev	0.00
VHDL - Scrolling Text on 7 segment Display	-0.34
VHDL expression is not constant	+3.61