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Rating Stats for

Jonathan Drolet

Rating
1550.32 (7,843rd)

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2,857 (59,149th)

Page: 1 2 3

Title	Δ
State machine with multiple inputs	0.00
why PCIe TLP header has "Last DW BE" and "First DW B...	0.00
Changing the modelsim.ini file (ModelSim)	-2.30
Multliplication of std_logic_vector with Floating Point	+3.55
Writing a Module Which Prevent Overwriting Previous Data in RAM	0.00
Unable to compare part of a std_logic_vector to a constant	0.00
What is the Intel Strata Flash Memory on Spartan-3E Starter Kit?	0.00
8 bit Ripple carry adder Port mappinng in VHDL	0.00
How to Get Audio Out via the Wolfson WM8731 CODEC on the Altera DE2...	-0.49
Store Previous Data in VHDL Process	0.00
vhdl code understanding, if there is modelsim error about possible...	0.00
How to enlarge the memory in Microblaze for software applications?	0.00
Can signals be used instead of hard coding values multiple times?	0.00
VHDL book example	0.00
VHDL - Designing a simple first order IIR filter	0.00
how I know the fpga_0_RS232_RX_pin of Atlys spartan-6	0.00
Sound generator on FPGA with VHDL code	0.00
Relation between LUTs, logic cell, logic elements, system gates	0.00
Drive input clock to output	+3.27
Parameterisable Black Box Modules, Parameterisable IP inside my own...	0.00
MicroBlaze is under RESET	0.00
Pulse Width Modulation using VHDL	0.00
What does SHR stand for in VHDL and how do you use it to shift to a...	0.00
Use of Xil_Out32 in Xilinx SDK	0.00
Write code that flip the nth bit	0.00
What is the difference between signed and unsigned addition in vhdl?	-0.43
Multiplication with a variable in VHDL	0.00
Image Processing Pipelining in VHDL	+1.53
Having trouble designing an architecture(schematic)	0.00
VHDL Is there a cleaner way to set specific bit, given the bit numb...	+4.44
"when others" line in VHDL case statement?	-3.10
Why are ports redefined when using components?	+4.25
VHDL if statements in process driving multiple outputs per if state...	+3.94
Verilog Xilinx - FPGA board - Cannot instantiate three multiple ins...	0.00
VHDL - Shift operation of N times with concatenation	+3.74
Exit a loop using external signal in VHDL	0.00
arctan function with cordic with vhdl	0.00
What's wrong with this VHDL code - BCD Counter?	0.00
Putting an enable input on a decoder (VHDL)	0.00
Bus timing constraints	+3.53
Testbench errors when using Xilinx Logicore Boxes	0.00
how to make the value of a register fixed	+3.83
VHDL, if statements, and process names	+3.65
How to Write A Mux With Several Inputs Without Creating a New Input...	+4.88
synthesizable asynchronous fifo design towards an FPGA	+3.96
What's wrong with this simple VHDL for loop?	-3.84
Is setting signal values to unitialized acceptable?	0.00
Targeting DSP slices on FPGA from HDL code for multiplication	0.00
VHDL code to find square root of number?	+4.36
Strange behavior of VHDL if statement	0.00