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Rating Stats for

Jan Decaluwe

Rating
1511.52 (61,462nd)

Reputation
2,046 (82,145th)

Page: 1

Title	Δ
MyHDL: Object type is not supported in this context	0.00
MyHDL: library use clauses in user-defined code	0.00
What is the need for a sensitivity list to be associated with a pro...	-0.13
Connect internal signal to output port in MyHDL module	0.00
Estimating area required by a VHDL implementation	+3.91
When should I use std_logic_vector and when should I use other data...	0.00
Difference between yield statement in python and MyHDL	+4.38
FSM state changes in Verilog	-3.77
Using wire or reg with input or output in Verilog	+4.10
How to split a two-digit number up in Verilog	-3.88
How to restart a Verilog simulation in Modelsim	0.00
How do these two modules differ in behavior	0.00
VHDL: Finding out/reporting bit width/length of integer (vs. std_lo...	0.00
Datatype problem in simple IF statement in VHDL	0.00
Design of "simple" VHDL module still drives me mad	0.00
Simulation vs hardware mismatch	-1.92
What is negation (not) of a bit vector in VHDL	+4.19
Array indexes to wide for array	0.00
Passing Variables to procedure in VHDL	-4.03
Verilog array syntax	+4.04
Ideas for a flexible/generic decoder in VHDL	+3.95
Unable to execute/run any vhdl code using ghdl	-3.73
Where can I find a definitive list of the ModelSim error codes?	0.00
How to interpret blocking vs non blocking assignments in Verilog?	+4.41