StackRating

An Elo-based rating system for Stack Overflow
Home   |   About   |   Stats and Analysis   |   Get a Badge
Answers and rating deltas for

Using wire or reg with input or output in Verilog

Author Votes Δ
Jan Decaluwe 11 +4.10
Ben Jackson 5 +0.80
toolic 4 -0.71
john_conner 0 0.00
Last visited: Sep 14, 2014, 5:07:29 AM