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Chiggs

Rating
1524.86 (24,079th)

Reputation
2,309 (72,931st)

Page: 1 2

Title	Δ
How do I specify the compare function of the scoreboard in Cocotb?	+3.99
verilog with cocotb : assign statement	0.00
Packed Structs in System Verilog VPI?	0.00
Aldec Riviera-PRO break simulation on SystemVerilog $error or $warn...	0.00
SystemVerilog parameterized functions in Quartus II	0.00
Randomize dut parameters in system verilog	-1.58
Is there a way to run freely available systemverilog testbenches on...	+0.33
Do all Flip Flops in a design need to be resettable (ASIC)?	-1.93
how to get rid of tr_db.log in uvm-1.2?	+4.34
Can Verilog variables be given local scope to an always block?	+4.34
Efficient use of ALMs (Adaptive Logic Modules)?	0.00
How can I achieve something similar to Xilinx' RLOC in Altera F...	+3.90
Convert Compressed Image into VHDL RGB Array	0.00
verilog multi-dimensional reg error	+0.00
SystemVerilog: How come the enum next() method cannot be used in a...	0.00
Access top level resources outside of hierarchy	+2.11
Modelsim / reading a signal value	-3.99
ModelSim simulation - modules not definied	0.00
Vhdl rising_edge statement not synthesizable	+0.01
How do you define backdoor access for fields which span two registe...	+0.31
Modelsim Optimization Issue	0.00
Place and route timing strategy	0.00
Quartus Programmer II TCL flash *.pof file	0.00
VHDL Quadrature Decoder: Sequential/Combinatorial Logic	0.00
using variable in for loop to specify index of an array in verilog	0.00
Initial iterator for generate for-loop	0.00
How can I make my parameterized bit widths cleaner?	+3.99
Width independent functions	-0.24
Verilog Wave Forms	0.00
Verilog testbench for fifo	0.00
Any built-in Linux methods for AXI-burst type devices?	+0.16
Unable to find bug in Simulator, because $display & Wave window...	0.00
Reset If-Else statement produces improper results	+2.24
Finding an unused index in a Verilog array?	0.00
Why is adding one operation causing my number of logic elements to...	+3.93
Why I get a syntax error when using typedef in verilog?	-3.60
Removing the need to reset the device before using it	0.00
Verilog/VHDL - How to avoid resetting data registers within a singl...	+2.01
PLI Verilog: how to restart a simulation	+3.99
How to send and receive bytes stream between PC and DE2 board	0.00
Snake game using FPGA (ALTERA)	+4.01
Distribution independent libpython path	0.00
Advance time in simulator using Verilog VPI	0.00
Reading and Writing to a file simultaneously	0.00
access dlopen flags	0.00
Export Xilinx ISE RTL/Technology Schematic into Netlist Text File	0.00
Simple Verilog VPI module to open audio files	0.00
VHDL: Is it possible to define a generic type with records?	+0.32
Estimating area required by a VHDL implementation	-3.91
Explicitly define how LUTs and slices are used in Xilinx XST tool?	-3.94