StackRating

An Elo-based rating system for Stack Overflow

Home | About | Stats and Analysis | Get a Badge

Rating Stats for

Matthew Taylor

Rating
1518.66 (34,748th)

Reputation
7,546 (21,052nd)

Page: 1 2 3 4 ... 11

Title	Δ
VHDL casting a custom Type signed integer to a std_logic_vector	0.00
Quartus Prime throwing an error at a $error command	-1.33
unnecessary register reset in FPGA	+0.45
SystemVerilog not recognizing constant: Error: Range must be bounde...	0.00
Defining different parameter value for simulation and synthesis	-0.03
Aggregate Ordering with Named Association	0.00
Assigning initial value to VHDL vector	0.00
I'm getting this error for my verilog code, "Illegal opera...	0.00
VHDL arithmatic operation between unsigend fixed point number (ufix...	-0.03
Verilog, how to do the same thing below if i got parameter?	0.00
HDMI Pass Through with RGB Switch Filter	0.00
Parameterized logic including module instantiation and so on	0.00
Cross-module reference resolution error - verilog checks for undefi...	0.00
`define in generate if statement	0.00
How does system verilog treat if statements in always_ff blocks	-0.03
output of 8 bits adder in simulation is xxxxxxxxx	-1.88
Array slicing in inside operator in system verilog constraints	-0.96
Difference between 1 and 1'b1 in Verilog	-0.87
For loop equivalent RTL description	-0.05
Multiplier via Repeated Addition	+0.47
Passing parameters between Verilog modules	+1.98
Verilog: Declaration error at define_state.h: identifier is already...	0.00
How to find amplitude and frequency of an incoming sinusoidal signa...	0.00
Function Overloading for 'high/'low	0.00
Bitwise operation between scalar and vector	0.00
Parse error in instantiating component-unexpected PORT	0.00
Does a constant use a register in an FPGA?	-0.53
In SystemVerilog, what does (.*) mean?	-0.54
VHDL use dependent generic type in port specification	0.00
How to store return value from $system("...") call in Sys...	+2.34
Can a function in verilog call another function?	0.00
Error with VHDL integer signal connecting Verilog integer input	+0.48
Is it possible to use packed structs with DPI	0.00
Compile + elaborate design with identical cell names	0.00
Pipelining an adder that sum 256, 20-bit words in Verilog?	0.00
System Verilog parameterise class with interface	+0.46
How to deal with parameter that is array of string in systemverilog?	0.00
How to write string values in Verilog testbench?	+1.85
forcing internal DUT signal from UVM driver	0.00
VHDL Simple Seven Segment Display on Basys2 FPGA board	0.00
Wait for input state change to start process	0.00
the difference between a[b+1] and a[b+1'b1]	0.00
If sensitivity list in VHDL is not synthesizable, why does it gives...	+0.50
What happens if I create an object of a class A but there also exis...	+1.86
Error (10395): VHDL Conditional Signal Assignment error at (146): c...	0.00
How does this SIPO Works?	+1.75
what are the uses of case 'inside's in verilog ? is it synt...	0.00
How I make an output logic signal a real output pin?	0.00
Is it possible to allow multiple drivers on a wire?	-0.00
Number of bits for a particular count of integer in Verilog	-1.02