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Rating Stats for

Matthew Taylor

Rating
1518.66 (34,748th)

Reputation
7,546 (21,052nd)

Page: 1 ... 9 10 11

Title	Δ
How to handle SystemVerilog-specific types in c and vice-versa?	-3.43
Why isnt this code in vhdl simulating anything?(testbench and design)	+3.94
Pass parameter during instantiation of ip core in vivado	0.00
Is it possible to shift more than 1 bit per cycle in verilog?	0.00
verilog bit shift with 1	-1.29
8 bit to 16 bit ALU conversion	0.00
instancing modules verilog	0.00
16-bit bitwise and in VHDL?	-4.11
How can I see a variable's value for debugging VHDL code in mod...	-3.85
Set VHDL foreign attribute based on generic	0.00
Verilog Multiple Constant Drivers	-0.07
Always in a task?	0.00
How to handle data going from a clock domain to another clock domai...	-3.42
Using clock and enable	-3.15
max_fanout property of Virtex-6 circuit is not applied	0.00
VHDL integer to string	-0.15
How to create synthesizeable delay?	+0.04
How to do matrix multiplication in Verilog?	0.00
Meaning of [->1] in system verilog property definition	+1.83
syntax error in verilog code ,near "<=": syntax error,...	-2.63
can you compare an int to a bus in verilog?	0.00
VHDL array concatenation of varyigng types	0.00
How can I reset this D-type counter in the attached Verilog-HDL code	-3.52
creating a linear search algorithm in vhdl	0.00
VHDL - coding error of value outside the clock edge	+4.84
Is it written in VHDL or Verilog	+1.81
VHDL Syntax Error: With-Select statement	+3.60
multiply two text file in VHDL	0.00
VHDL - comparing signals (integers) in IF-statement	0.00
2D Unconstrained Nx1 Array	+3.79
How to stop a simulation by timeout?	+3.03
VHDL Counter ones errors	0.00