StackRating

An Elo-based rating system for Stack Overflow

Home | About | Stats and Analysis | Get a Badge

Rating Stats for

Matthew Taylor

Rating
1518.66 (34,748th)

Reputation
7,546 (21,052nd)

Page: 1 ... 8 9 10 11

Title	Δ
What does <= operator do in this code?	0.00
how to describe an 8-digit seven-segment display with Verilog	0.00
How can I write C for loop in VHDL-AMS?	+3.62
call by reference in verilog code	+3.21
Verilog shift register of parameterized length	0.00
Alternate way for port map in process?	0.00
VHDL for loop always give me the same value	0.00
Encoder VHDL Code	+0.08
Begin:comparison Statement in procedural block	+4.89
Condition: Logical state of multi-bit packed array	+0.05
defparam inside generate block in veilog	0.00
urandom_range(), urandom(), random() in verilog	+0.40
Unknown Error during synthesis of AXI IPs	0.00
Integer input ports in verilog simillar to vhdl?	-0.44
How can assign a synthesizable string to a byte array in SystemVeri...	0.00
conditionally calling a module using case statement	+3.65
How can I use seperate digits in seven segment display in basys 3 i...	+3.89
VHDL 3-bit u/d counter	+0.07
VHDL Order of options in case statement	+4.14
Shift left register using VHDL shift operator : sll trouble	+3.91
Hamming (7,4) Code - Finite State Machine	0.00
ModelSim SE 5.7: unexpected 'Z' and 'X'	0.00
PAD symbol "r<3>" has an undefined IOSTANDARD - Ver...	0.00
ERROR:Xst:827 = Signal count cannot be synthesized, bad synchronous...	0.00
When should I use reg instead of wire?	+3.72
Errors with VHDL Script Syntax	-3.75
VHDL: genric map setup	0.00
VHDL: Adding operations to 8-bit ALU	0.00
Verilog : For loop inside an always	-2.43
How to make a generic NxM signed array multiplier using verilog?	0.00
VHDL constant in generics	-3.25
Vhdl signal declaration usage	0.00
assertion for holding the reset for a long time	-0.18
Why do we use Blocking statement in Combinatorial Circuits designed...	+1.10
ALU with Structural VHDL??	0.00
How can you deal with BOTH signed and unsigned numbers in VHDL?	-0.07
Verilog Oracle, Expected Value doesn't work properly	0.00
Component Instantiation vs Entity Instantiation in VHDL	+4.01
Input assignment in testbench and output values (ghdl and gtkwave)	-3.80
Decode name of packed struct member based on bit position	0.00
Automatic Verilog code generation issue	+0.52
Memory code errors in Verilog	0.00
Error in Function evaluation	-3.41
Converting VHDL to Verilog	+3.94
Using 2 different 7 segment display to display a 4-bit 0 to 15 coun...	0.00
Line 141. parse error, unexpected IDENTIFIER	+0.30
Value changes based on clk doesn't work for random numbers	+5.35
Define 2-dimensional array of wire in verilog	0.00
Verilog module cannot calculate a&b and a\|b	+2.04
Errors in VHDL code	0.00