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Rating Stats for

Matthew Taylor

Rating
1518.66 (34,748th)

Reputation
7,546 (21,052nd)

Page: 1 ... 7 8 9 10 11

Title	Δ
VHDL clocked LED Sequence Part 2	0.00
How can I determine the register bit widths correctly?	+0.22
Package procedure calls for testbench stimulus	+2.39
VHDL clocked LED Sequence	+0.47
verilog fwrite output bytes	+0.24
How to initial unpacked array with another unpacked array	-0.06
Is there automatic vector width coercion in Verilog?	+0.46
Strange latch behavior in VHDL code	0.00
Systemverilog coverage point for multiple of n	0.00
Why I can not input value to inout type?	0.00
How to convert Verilog (.v) project to EDIF(.edf) format?	0.00
I want to use the ram in my FPGA Altera DE1-SOC, am I taking the co...	-0.54
Verilog "In, out, or inout does not appear in port list"	0.00
which procedural block executed first, in SystemVerilog?	0.00
What is the difference between implication (->) and ##0 in SVA?	-0.54
Why is using NOT with implication a bad idea in SVA?	0.00
SVA concurrent array comparision	0.00
Prefered syntax for verilog module declaration	-0.48
From hard coded if else if to configurable if else if loop	-0.98
Incomplete sensitivity list in VHDL with Sigasi editor	+0.53
explanation of arrays in systemVerilog	0.00
how "A loop" complete in a clock	0.00
generate inside generate verilog + error near generate(veri - 1137)	0.00
Why am I getting an "invalid aggregate" error when trying...	0.00
Generate custom waveform in verilog	0.00
Recursive self-instantiation component [VHDL]	0.00
How to pass information from inside sequence/property to the outsid...	0.00
What is the difference between using an initial block vs initializi...	-0.37
SystemVerilog: How to create an interface which is an array of a si...	-0.03
VHDL 2008 > generic package in an entity: error expecting BASICI...	0.00
Two outputs values in a mod operation using vhdl	0.00
Choosing element from array in VHDL	0.00
FT600 Interfacing with FPGA	0.00
Different flipflops - different outputs for one reset input	-1.58
SVA Property for a simple waveform	0.00
VHDL weird behavoir of an array of unsigneds	0.00
Verilog, using enum with don't cares	+0.32
Verilog signed multiplication: Multiplying numbers of different siz...	0.00
How to write an integer to stdout as hexadecimal in VHDL?	-2.10
How to generate asceding values during randomisation	-1.98
How to generate asceding values during randomisation	-1.98
Flip-flop and latch inferring dilemma	+3.93
What is the best practice to handle invalid or illegal combinations...	0.00
Verilog - creating a timer to count a second	-2.91
Assigning a signal to variable and a variable to a signal	0.00
Why it's code not compile?	-0.41
Systemverilog: $realtime display for different timescale precision	0.00
VHDL: Assigning a smaller std_logic_vector to a bigger one	0.00
Can't resolve multiple constant	0.00
How to write property for formal verification?	-0.33