StackRating

An Elo-based rating system for Stack Overflow

Home | About | Stats and Analysis | Get a Badge

Rating Stats for

Matthew Taylor

Rating
1518.66 (34,748th)

Reputation
7,546 (21,052nd)

Page: 1 ... 5 6 7 8 9 10 11

Title	Δ
In Verilog and VHDL, what exactly is the difference between `logic[...	0.00
Verilog - confusion between \|\| and + operator	-0.52
VHDL Testbench : Output not changing	0.00
Large Array Initialization to 0	0.00
multidimensional arrays in VHDL	0.00
How to assign inconstant value to reg in Task , In Verilog?	0.00
Can't handle registered multi driver	+0.31
Arithmetic mean of a register in vhdl	-0.26
Error declaring and using signed complex quantity using enumerated...	+0.48
VHDL program that chooses which operation to perform	0.00
Verilog model sim	-0.03
Query for VHDL synthesis for IC Design (Not FPGA), specifically in...	0.00
VHDL Syntax error in user defined package RNG for genetic algorithm...	0.00
Is it necessary to seperate combinational logic from sequential log...	+0.23
VHDL-2008 initializing ufixed gives error in modelsim	0.00
Where to install compiled device libraries for functional simulatio...	0.00
VHDL error "Process clocking is too complex."	0.00
Spring social Authorisation Exception with Facebook	0.00
Entity does not match component port	0.00
Signed Hexadecimal Value Representation in Verilog	0.00
Undefined Output	0.00
Why latch doesn't get inferred for following logic?	0.00
Xilinx VHDL latch warning troubleshooting	0.00
RANDOM 0, 1, -1 IN VERILOG	+0.37
Should i be using the uvm_component/object_utils macros	-0.39
Does SystemVerilog support global functions?	0.00
Implementing a counter in VHDL	-0.97
Delaying the clock by a fraction of the period	+0.49
implementing a flip-flop with concurrent statement	0.00
Need help in Reading contents of memory array and get a count in vhdl	0.00
How to deallocate an acces type variable before returning value at...	-0.76
Difference in timing while getting values from ROM or RAM	0.00
Parameterizable VHDL subtypes	-0.04
What is "net" in HDL synthesis	0.00
Verilog vector inner product	0.00
How to convert integer to string with leading zeros in vhdl?	-1.24
How to convert integer to string with leading zeros in vhdl?	+0.01
Issue with simulation timing	0.00
VHDL Error : Choice in CASE statement alternative must be locally s...	-1.62
Where can I write concurrent assertion in monitor?	-0.51
active low reset in Port Mapping	+1.39
how to use Clocking block in verilog	-0.66
Associative array with wildcard in system verilog	0.00
Do I need an else statement in a sequential always block?	0.00
SystemVerilog Interface array with different parameters	0.00
verilog declaring a not wire	0.00
why moore circuit requires an extra state compared to mealy	0.00
Can't make the required diagram	0.00
invoking modelsim simulator through perl script	0.00
Diffrence between simulation and synthesises of verilog always block	0.00