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Matthew Taylor

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1518.66 (34,748th) 		Reputation
7,546 (21,052nd)
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how does a variable to be decided it's value without it's i... 0.00
Regarding verilog always blocks +1.20
Error (10500): VHDL syntax error at lab_06.vhd(54) near text "... 0.00
What does the variable name in the register declaration indicate (V... +1.82
unexpected errors in verilog 0.00
Exporting task of an instantiated module -1.58
Switch on LED after receiving Ethernet packets 0.00
Can I optimize my verilog code using Synopsys DC and bring it back... 0.00
VHDL signal assignment within a process not behaving correctly? 0.00
Entity syntax in VHDL 0.00
systemverilog assertion - how to ignore first event after reset -0.53
Carry/Borrow in VHDL ALU +0.48
How to toggle a std_logic between 1 and 0 0.00
divisor for std_logic_vector VHDL 0.00
Error: D:/velilog/bubu.vhd(3): near "clock_in": (vcom-157... 0.00
VHDL arithmatic shift_left +2.23
return unconstrained array in vhdl 0.00
How does the synthesizer decides on bitwdith for intermediate resul... 0.00
fseek not working in system verilog 0.00
Testbench of SR Fliflop in VHDL -1.25
Verilog - If Condition -0.59
modelsim says : "near ")": (vcom-1576) expecting IDE... 0.00
what is the equivalent of logical and (&&) in vhdl? 0.00
SystemVerilog - With an enum can you have a range? -0.55
how to delay a signal for several clock cycles in vhdl -1.16
Gate instantiation in if else statement in verilog -0.02
ModelSim on Ubuntu +0.48
vhdl Relational Operations 0.00
VHDL can't matching context of call for to_unsigned in user def... -0.51
syntax error near behavioral -1.70
Alternate signals for test bench without manually typing out all ti... +0.45
SystemVerilog - how to use string as event or as time? +2.39
Slice even/odd elements in VHDL -0.11
signedness vs bit size 0.00
SV assertion based on event trigger 0.00
Component instantiation error 0.00
Function clogb2() generated by vivado can't synthesize with loo... -0.74
Syntax error, unexpected non-printable character with the hex value... 0.00
strange edge detection or something other? +0.18
What is a LINT/synthesis safe statement to throw an error at compil... -0.64
VHDL 2D Array Initialization using single Index 0.00
VHDL Array Initialization Error 0.00
Verliog: Different Outputs when using an intermediate variable for... 0.00
systemVerilog - How can I convert int unsigned to array logic? 0.00
Difference between unsigned and std_logic_vector 0.00
What happens when we assign 2 values to same variable? 0.00
Maximum bit-width to store a summation of M n-bit binary numbers -0.54
Do VHDL signal assignments set destination value or reference? 0.00
VHDL fsm error - near "when": (vcom-1576) expecting END +0.31
Error (10278): Verilog HDL Port Declaration error at TrafficLight.v... 0.00