StackRating

An Elo-based rating system for Stack Overflow

Home | About | Stats and Analysis | Get a Badge

Rating Stats for

EML

Rating
1501.64 (386,659th)

Reputation
6,021 (27,076th)

Page: 1 2 3 4

Title	Δ
Verilog: tristates for synthesis, and difference between conditiona...	0.00
vhdl to verilog bintobcd converting	0.00
What is the exact criteria for an inout port, when sometimes inout...	+0.41
How to reuse multiple always blocks in Verilog	-0.84
How to find the size of a reg in verilog?	0.00
Verilog Error: Object on left-hand side of assignment must have a v...	+0.17
object <name> is not declared in verlog	-1.72
VHDL latch issues (flip-flops are not an option)	0.00
Why do we use REG in FGPA / VHDL / VIVADO?	0.00
Can I reuse a signal that is assigned values within a different pro...	+0.50
How to know direction of signal in Schemetic Tracer of simvision?	0.00
What's the difference in process handling	+0.51
Is there anyway to read through a file multiple times in vhdl using...	-3.85
Instantiate VHDL in Verilog with generics containing std_logic	0.00
VHDL signal assigement doesnt work for no apparent reason	0.00
How does a 32:8 mux work?	0.00
sensitivity list in process in vhdl	0.00
Number of flip flops generated in vhdl	0.00
What is the use of transport in VHDL?	+3.97
Verilog HDL: Having nested if inside reset condition is synthesizab...	0.00
Calculate fmax of Altera design	0.00
Instantiation of multi architecture vhdl enity in verilog testbench	0.00
How to include jQuery in HTML?	+4.16
Show (generated) HTML only, no Javascript	-4.15
Woocommerce: how do I add metadata to a cart item?	0.00
Programmatically adding a signature to an email	0.00
WordPress: hooks into mouse events?	+2.16
How can I test pages with links without pushing changes to my live...	-3.81
Implementing an intelligent relay with an SMTP server/client	0.00
Using URL rewrite to access menu item on a static site?	0.00
JavaScript: Is it possible to handle server errors from `form.submi...	0.00
How do you move non-zero elements in an array to the top in a singl...	-3.83
Javascript: can't see server cookie	0.00
Interaction between unselectable and undraggable in Firefox	0.00
Parameter array in Verilog	-3.62
Verilog module order	-3.92
Verilog shift extending result?	0.00
verilog always@(*) nonblocking assignment	+3.78
sequential vs combinatorial logic (Verilog and VHDL)	-3.99
Strange component in quartus RTL viewer using verilog	+4.78
Verilog two dimensional array syntax	-4.04
Unexpected delay in Verilog adder	+0.45
Verilog 'assign' statement	-2.11
Define register in verilog	0.00
warnings while running code in xilinx	+4.42
Generics in hardware description language	+2.99
VHDL or verilog SR latch	+3.72
Floating Point Adder - Optimization of comparator	-0.02
If statements causing latch inference in Verilog?	+2.02
Why put delays in Verilog even for some simple assignment?	+4.25