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Rating Stats for

Rich Maes

Rating
1490.95 (4,400,399th)

Reputation
651 (220,629th)

Page: 1 2

Title	Δ
Verilog/SystemVerilog inferred latch in case statement	+4.20
How can I improve my code so I don't get timing errors?	+4.10
How can I investigate failing calibration on Spartan 6 MIG DDR	0.00
Verilog 4 bit comparator = not working properly	+0.04
How to properly program a "function" in verilog, for this...	-0.17
FPGA Timing issue between Sys_CLock and Signal-Tap	0.00
First non-zero element encoder in Verilog	-3.64
Clock Domain Crossing for Pulse and Level Signal	+0.00
Verilog Decoder with single inputs/outputs, not vector	-0.05
" top level design entity is undefined" ... what does it...	0.00
DPDK compiler error on fedora 23	0.00