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Rating Stats for

Russell

Rating
1504.18 (176,279th)

Reputation
2,453 (68,773rd)

Page: 1 2 3

Title	Δ
For loop, arrays, step motor VHDL	-3.49
Propogation delay in sequential logic	0.00
vhdl tructural statement inside a sequential architecture	+2.63
VHDL Pullup Resisters	+0.62
Latch duplication in technology schema (vhdl)	+0.18
Where is the latch?	-3.21
"Invalid Module Instantiation" Error in Mealy sequence de...	+4.46
Accessing 2 elements of the same array in VHDL	+0.53
Triggering signal on both edges of the clock	0.00
Controlling an LCD in VHDL on spartan 6	+4.30
assigning output to vdd in verilog	0.00
VHDL state machine differences (for synthesization)	-0.57
Generate NGC for custom VHDL module in IPCore Xilinx	-3.69
4bit multiplier in verilog without multiplication operator	0.00
Two input signals at the same always block	-1.59
How to ignore output ports with port maps	+4.23
Crossing clock domains within a device	0.00
Using variables in case statement, VHDL	-3.77
Conditional UCF statements or conditional UCF file inclusion	-1.96
Signal not changing state in iSim	+0.62
Behavioural logic sequential, code cannot work?	-3.14
Case statement in Vhdl converter	+0.14
How to read from a specific line from a text file in VHDL	-3.18
Division in VHDL (int/float)	-3.84
Synthesis of Image processing unsing VHDL takes lot of time	0.00
JK Flip Flop Debugging Iteration Limit error in VHDL Modelsim	-1.95
How to output array elements in random order using VHDL	-2.64
Why is my serial communication not working?	+3.88
Launch Modelsim from Cygwin?	0.00
Why does the LCD of a Spartan 3AN is not working?	0.00
test bench multiple architectures	-4.10
Structural Architecture code in vhdl	0.00
Write a loop that reads ten numbers and then outputs them	-0.47
Xilinx ISE with ModelSim SE Linux configuration	0.00