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Answers and rating deltas for
How to make an empty datatype or conditional field in SystemVerilog
| Author | Votes | Δ |
|---|---|---|
| dave_59 | 0 | -0.50 |
| Serge | 0 | +0.39 |
| Tudor Timi | 0 | +0.11 |
Last visited: Dec 1, 2017, 2:11:24 AM