StackRating

An Elo-based rating system for Stack Overflow

Home | About | Stats and Analysis | Get a Badge

Rating Stats for

Serge

Rating
1505.96 (123,352nd)

Reputation
3,927 (42,729th)

Page: 1 2 3 ... 12

Title	Δ
SystemVerilog Merging Events	+2.34
I implemented an RV32 using verilog. But the output is always 0, i....	0.00
Casting wire vector to integer in verilog	0.00
Error (10170): Verilog HDL syntax error at Test1.sv(29) near text:...	0.00
How to make an array with all the enum values in system verilog?	+2.37
Why are "if..else" statements not encouraged within syste...	0.00
If the testbench and test are top-modules how to pass the instance...	0.00
How does adding 1'b1 to 8 bit reg work in Verilog?	0.00
Using tasks declared in interfaces within a package	0.00
custom command in git submodule.<name>.update	+2.09
Verilog wire to register	0.00
Parameterizing a SystemVerilog interface for optional array of a po...	0.00
Can Pass by Reference also be called as Pass by Pointer?	-1.11
Generate an array (of variable size) only from parameters	0.00
what is the type of '0 as opposed to 'b0 in systemverilog?	+2.39
What is the difference between the symbol '->' and '...	0.00
wire output shows nothing in verilog simulation code	0.00
Illegal concatenation of an unsized constant	-1.63
Two to one mux in Verilog giving errors for unable to bind for a ca...	0.00
Questions about returning char* and memory	+0.76
Strange behavior when running a piece of verilog code on modelsim	0.00
Rotations Operations for 16bit ALU using multiplexers (updated ques...	0.00
How to compile a file with compiler directives (`ifdef) and differe...	0.00
System Verilog Loops	0.00
Can posedge in verilog be used only on clock?	+2.40
Bit slicing with variable width in SystemVerilog	+2.40
parameter based typedef in system Verilog	+0.51
Verilog How to change wire by bit with clock?	-0.52
Confused as to why increment function doesn't actually incremen...	0.00
What is the difference between using assign and always block for co...	-1.60
how to preset the register arrays in Verilog?	0.00
2^n to n priority encoder w/ continuous assignments	0.00
How to define multiple modules sharing same data bus in SystemVerilog	0.00
How can I run this Verilog module sequentially?	+0.50
How do I compose strings for later serial transmission?	0.00
verilog error ... (vlog-2110) Illegal reference to net array	0.00
How to write a behavioral level code for 2to4 decoder in verilog?	+2.75
What is the difference between begin end and fork join with respect...	+0.33
Cutting a string when a specific character is found	+2.66
Linting: Comparing Verilog Parameter and Constant String	+0.42
inout port with real datatype in systemverilog	+2.46
Verilog Include File Conditionally	+0.47
Why does pointer to object not work as expected?	0.00
C++ How to find pair of 3 integers in vector< pair<int, pair&...	+0.16
Cannot break the forloop	-1.37
why I get Syntax error near "else" in assertion in verilog?	+0.02
Verilog error handling two posedge signals in "always" bl...	0.00
How to prevent inferred latch and latch unsafe behavior in Verilog?	+0.51
How to set a signal at both posedge and negedge of a clock?	0.00
Cause of inferred latches (not else or default statement) in Verilog	+0.64