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Answers and rating deltas for
Nested if (rising_edge(clk)) statements in VHDL
| Author | Votes | Δ |
|---|---|---|
| Martin Thompson | 5 | +0.41 |
| davidd | 1 | -0.03 |
| Brian Carlton | 1 | +0.75 |
| Nikolaos Kavvadias | 0 | -3.97 |
Last visited: Sep 14, 2014, 5:07:29 AM