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Rating Stats for

Martin Thompson

Rating
1487.04 (4,454,104th)

Reputation
14,667 (9,652nd)

Page: 1 2 3 ... 12

Title	Δ
A debugger device fails to connect to target via CAN	0.00
Looping in vhdl	-1.87
How to check that microprocessor is Altera Nios?	-0.49
Is or-wired can bus used?	0.00
Check synthesis output online?	0.00
Clock source Selection for CAN bus Controller	0.00
Queues in TI-SYSBIOS	0.00
Implementing a Digital Accelerometer Using I2C and Arduino Uno	0.00
FPGA reached the limit of USB WireIns	+0.52
VHDL what is more efficient to use : an integer with range or a std...	-1.57
How a CAN Bus addressing works?	+0.28
Arduino as serial 'snoop' tool for 77 bits at 100k baud?	0.00
Using entities from another file in VHDL	0.00
Where does the error stem from in the process?	+0.52
Creating a list of found Mifare Tags with arduino?	0.00
VirtualWire - Send Integer Array	0.00
Convert "AA" to 0xaa in arduino	0.00
Baud Rate Clock VHDL -- floating point exception error and/or style...	-0.46
Persisting an output in comb logic block	+0.14
How to test algorithm performance on devices with low resources?	-0.47
How to eliminate ACK slot error in CAN?	0.00
VHDL nested case statement for some case options	+0.29
Exact software synchronisation on vsync pulse	0.00
VHDL error please	+0.02
VHDL architecture with processes	-1.88
Understanding Clocks	+0.01
SET A VALUE TO PIN BY MONITORING SAME PIN IN VHDL	+0.13
Cortex-A5 unaligned access exception	0.00
How to program a CAN-BUS arduino shield to control car windows?	+0.01
Use DCM for generate clock of 78 mhz from 100 mhz clock	-0.25
What is the need for a sensitivity list to be associated with a pro...	-0.47
VHDL Simulation Error	-0.49
Do GPU's have physically reconfigured parts like FPGAs?	0.00
VHDL invert if to reduce nesting	-0.49
VHDL RAM 256x8 bit	0.00
VHDL: Type of "variable" is incompatible with type of <=	-1.62
(VHDL) How to assign a summation result partially in one clock	-1.60
How do you program a television	0.00
Design of a VHDL LUT Module	+0.27
VHDL: assigment of paramaterized busses in a process	+0.01
how can I use an infix expression in a case statement in VHDL?	+0.00
Merge C program and VHDL bitstream via "make" (i.e. using...	-1.45
VHDL - How to implement AdHoc network	0.00
How to instanciate a component for generation multiple component pa...	+0.01
VHDL - How do you connect 1 output-bit to several 1-bit signals?	+0.20
Connecting ports by name in VHDL, UCF-style	+0.39
Intermediate representation for FPGA compilers	0.00
How to wait on multiple signals	-0.40
PCIe JTAG for (re)programming a PCIe board	0.00
Cortex-A9 Cache Parity	+0.00