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Rating Stats for

Martin Thompson

Rating
1487.04 (4,454,104th)

Reputation
14,667 (9,652nd)

Page: 1 ... 10 11 12

Title	Δ
Looking for library declaration of IP Module	0.00
Reset an Altera M9K's content to 0 (power-up value)	0.00
In image processing, what is real time?	-2.76
Simple State Machine Problem	+3.66
Algorithms needed on filtering the noise caused by the vibration	+1.72
Wrapping and switching between similar entities in VHDL	+3.70
Redundant loop inside a process (VHDL)?	0.00
Import Code from FPGA Board (Spartan 3E)	0.00
VHDL constant initialisation	+0.03
process a signal from a .wav and turn it into binary data	+4.38
Generating a pure sine wave as output form FPGA using VHDL code	+4.10
Signals and Variables in VHDL (order) - Problem	-2.15
Configuration Management for FPGA Designs	0.00
JIT-ing on FPGAs?	+3.64
Professional VHDL IDE?	+4.01
or_reduce functionality	0.00
include floating point library in vhdl	+3.66
FPGA Filter Project	+0.26
Should you remove all warnings in your Verilog or VHDL design? Why...	-2.31
Hardware representation for arrays in VHDL	+1.94
verilog modelsim fpga	-0.93
Comparing FPGA with ASIC design	-3.89
VHDL conditional generation from makefile	-3.07
FPGA Programming and how does IP Core licensing work?	+3.85
Changing time mode in a Digital Clock from 12HR to 24HR in VHDL	0.00
How to read data from rom_type in VHDL?	0.00
DSP Algorithms Book	+1.38
How to generate serial signal from string?	-4.11
Getting started with HDLs from regular programming	+1.96
What is the best method for object detection in low-resolution movi...	0.00
Java GUI amd FPGA	-0.12
Overflow bit 32Bit ALU VHDL	-0.09
How does a TABLE work in AHDL?	0.00
Experiences with Test Driven Development (TDD) for logic (chip) des...	+4.06
VHDL How to add a std_logic_vector with a std_logic signal together?	+4.01
How to share register and bit field definitions between a device dr...	0.00
SURF and SIFT Alternative Object Tracking Algorithm for Augmented R...	0.00
Random number generation on Spartan-3E	0.00
PIR sensors + Arduino + Python + email alerts	0.00
Finding the next in round-robin scheduling by bit twiddling	0.00
Best way to approach FPGA Device Requirements	0.00
Mips calculation for embedded software	0.00
Is low-level / embedded systems programming hard for software devel...	0.00
Power Efficient Software Coding	0.00