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Rating Stats for

Martin Thompson

Rating
1487.04 (4,454,104th)

Reputation
14,667 (9,652nd)

Page: 1 ... 9 10 11 12

Title	Δ
How to obtain a absolute of a number in Xilinx Simulink?	0.00
DBPSK Demodulation in Simulink using Xilinx blockset	0.00
Single Port RAM in VHDL?	-2.46
Use a generic to determine (de)mux size in VHDL?	+3.55
What are best practices for optimizing pipeline throughput for fpga...	+3.63
quartus how convert four input to two inputs in block?	0.00
Design Flow to create a bootable SPI Flash (PROM File) for a Xilinx...	0.00
Problem handling signals in SystemC simulation application	0.00
Obtaining motion vectors from raw video	-1.56
unable to load the haarcascadeshaarcascade.xml in opencv	+3.46
How do I return a printf statement if the user inputs nothing?	-1.09
VHDL mux implementation?	+3.19
VHDL syntax for arrays of clocks (accepted by synthesis but not Act...	-4.63
FPGA timing question	+1.54
Hardware: Shortest delay to send an ouput signal using windows	0.00
Debugging VHDL: How to?	-3.51
Are VHDL character substitutions ever used in real life?	+4.05
Calculate how many ones in bits and bits inverting	+3.29
Tips for successful decryption	-0.67
What hardware or software solutions can be used to prevent of stack...	-4.94
How to sub with matched groups and variables in Python	+3.42
Negative Disparity Values?	+3.47
RSA Sign: OpenSSL	+4.52
Can I use a variable inside a generate statement?	0.00
Simple VHDL 4 to 1 MUX testbench is hanging	+3.48
Interfacing between ISE and EDK projects	0.00
Equivalent of #ifdef in VHDL for simulation/synthesis separation?	-1.08
What are the requirements to meet in order to ISE auto infer ram bl...	0.00
using divider core from xilinx	0.00
Python: Code for VHDL Code Generator	+3.49
Whats wrong with this VHDL code	-0.16
Automatic Cropping of Images(Automatic indentification image vs bac...	-4.13
What is negation (not) of a bit vector in VHDL	-2.28
Unable to execute/run any vhdl code using ghdl	+3.73
GHDL and VHDL - input for executable	0.00
Mixing sound files of different size	-4.68
SRA can not have such operands?	+3.71
Delta-sigma DAC from Verilog to VHDL	0.00
FPGA efficient (a)synchronous resets	+3.61
VHDL process style	+3.51
TAP (Test Anything Protocol) module for VHDL	0.00
Modelsim: how to setup 27 MHz clock	+4.01
How is a variable shown in a RTL viewer in Quartus?	0.00
Preserving the widths of ports	-3.86
adding '1' to LOGIC_VECTOR in VHDL	-0.23
Reading OUT ports for debugging	-0.43
The signal <n1<1>_IBUF> is incomplete	0.00
Problem with net instantiation	-2.33
Error adding std_logic_vectors	-0.30
Logical Operator problem VHDL	-1.74