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Rating Stats for

Martin Thompson

Rating
1487.04 (4,454,104th)

Reputation
14,667 (9,652nd)

Page: 1 ... 7 8 9 10 11 12

Title	Δ
Inactivity Kill-switch for SystemVerilog Testbench Simulation (VCS)	-0.08
Xilinx ISE 9.2 and programming FPGA	+0.03
Opinions and facts on multiplexer select in implemented VHDL code.	0.00
Cosine in floating point	-0.63
VHDL STD_LOGIC_VECTOR Wildcard Values	+0.43
VHDL driving signal from different processes	+0.17
shift a std_logic_vector of n bit to right or left	+0.47
when a signal must be insert in the sensitivity list of a process	+0.23
fixing bit width mismatch	-0.07
Always block being ignored	-0.06
Which is the most efficient operation to split an integer to two ch...	-2.14
VHDL and FPGA's	-0.07
Reading or writing multiple files using vhdl textio	+0.42
How to implement deterministic malloc	-0.14
What are minimal compilations steps to start new simulation after c...	0.00
How to do the same thing as the "compile all" button in M...	0.00
Developing A MIPS Processor using VHDL - any good tutorials?	-0.39
VHDL ALU undefined value	+0.48
Xilinx ISE build time and already compiled modules	-0.57
signal vs variable	+0.45
fixed point conversion from a real variable in vhdl	-0.07
"Unclocked" sampling and latches in VHDL	-0.55
Incrementing an internal signal	+0.45
Undefined output of Ring Counter Test waveform	-0.07
Passing Generics to Record Port Types	0.00
Matlab function/script to convert a real number to a hexidecimal si...	0.00
how to delay a signal for several cycles in vhdl	0.00
RGB palette designated for ordered values	-1.63
Error : Identifier 'q' is not readable in architecture of T Flip Flop	+0.44
Does the synthesizer care about one or two processes?	-0.41
Stopping the ARM Cortex A8 CPU on Android device	-0.09
How to write real data type into a file in VHDL?	-0.39
Parallel processing on FPGA. How to start with?	+2.18
Combinational implementation of hashing algorithms	-0.56
Detect Stack overflows	-0.53
Suggestion over a simple FAT16/FAT32 read/write implementation	0.00
Linux RTOS sleep() - wakeup() for timer task	+0.78
How can I average a subset of an array and store the result in anot...	-2.49
Reprogramming DMA start address using STM32F103 microcontroller (Co...	0.00
How to think about digital circuit design	+0.57
Define a method for record in vhdl	-0.08
questions about self-defined Gaussian blur using convolution	0.00
Unable to Acces GSM modem via usb to Serial cable	0.00
Trends in Flash memory and SRAM for embedded (avr / msp microcontro...	0.00
How do I get the width/height of a 2d array being pointed to with m...	-1.66
When do signals get assigned in VHDL?	-0.08
Optimizing RGBA8888 to RGB565 conversion with NEON	-0.27
Hexadecimal number on seven-segment	-0.02
downto vs. to in VHDL	+0.07
better way of coding a RAM in Verilog	-1.27