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Rating Stats for

Martin Thompson

Rating
1487.04 (4,454,104th)

Reputation
14,667 (9,652nd)

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Title	Δ
About verilog flip flop delay	-2.05
Difference between sparse and dense optical flow?	-0.56
Bitwise ANDING Of Two STD_LOGIC_VECTORS	-0.57
if elsif vhdl behavior	-0.57
implementing fixed-point multiplier in verilog	0.00
for loop executes only 1 time	-0.41
How are shifts implemented on the hardware level?	0.00
How to print a number using Verilog and Altera DE2 board's VGA?	0.00
Float and double rounding in C	+1.20
Can I have conditional constants in VHDL?	+0.44
Is it possible to write type-generic entities in VHDL?	+0.44
Incompatible modes for port vhdl	0.00
Empty string ends for loop	+0.59
How to get rid of a fitter warning about LVDS complement pin?	0.00
Short VHDL for loop code i dont understand	0.00
VHDL Method Call	-0.54
VHDL If Statements	+0.49
Can't compile a self programmed function on ModelSim	0.00
How to make MSP430 Sleep in mode 4?	+0.44
Simple adding don't work, timming issue	+0.46
VHDL Functions requiring additional LEs?	-0.10
Arduino Sketch compiles and then freezes upon uploading	0.00
VHDL: can not have such operands in this context (sobel filter)	+0.44
system report of emedded system created through Xilinx XPS	0.00
How to filter keyboard events?	-0.06
VHDL: Assigning elements from a 2D array to 1D array	0.00
How to do a bitwise AND on integers in VHDL?	-0.05
How to recompile GHDL source code	0.00
Why having this as a separate process causes all sorts of weirdness	-0.04
Greatest common divisor VHDL FSM	-0.11
How to disable XST FF/Latch trimming or hide warnings about it	0.00
How to measure the speed of an Arduino function's execution?	-0.46
Is there a beautifier/code formatter for VHDL?	+0.44
How to provide region of interest (ROI) for edge detection and corn...	0.00
Writing the main program of a D flip-flop	+0.45
Programming an FPGA?	+0.47
In VHDL when is the right time to use a Process statement?	-0.45
VHDL function does not compile	-0.08
VHDL: component port to entity port, how does it know what is what?	-0.58
VHDL: signals and ports on which side of the "arrow" =>	+0.43
Successful FPGA application for HPC, e.g. on a cluster with InfiniB...	-0.22
Arduino encoder interrupts corrupting serial data	-1.05
vhdl ram module and use of registers	+0.20
VHDL compiler exiting error	0.00
Is there a better way to re-write a BCD_counter in VHDL code with l...	-0.55
Easy AES in VHDL	0.00
FreeRTOS stay in infinitly in for loop for semaphore in vListInsert...	0.00
Regarding CAN bus	-0.40
Software PWM without clobbering the CPU?	-0.52
Is it possible to Connect micro controller pins direcltly to CANcas...	-0.09