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Rating Stats for

Martin Thompson

Rating
1487.04 (4,454,104th)

Reputation
14,667 (9,652nd)

Page: 1 ... 4 5 6 7 8 ... 12

Title	Δ
Verilog Program Editor and Compiler	-0.53
Libm has no trigonometric functions	-1.84
How can I speed up my math operations in VHDL?	+0.13
How to access text files at synthesis level	-0.03
Maximum speed in pipeline modelling in vhdl	+0.04
Errors during synthesis	0.00
std_logic_vector vs. integer synthesis in Xilinx vhdl	-0.02
Register with enable	-0.52
What are tsetup and thold in VHDL?	-0.03
VHDL for loop type error and shift error	-0.55
Can't perform logic operations on unsigned in VHDL?	-0.47
1Hz clock for a D FlipFlop VHDL	+0.25
how to represent sequential algorithm in VHDL	-0.22
Xilinx VHDL Multicycle constraints	0.00
VHDL wait on multiple signal	+0.53
How can I create a latch in Verilog	-0.89
VHDL - Debounce Button Press	-0.29
VHDL: variable and process	-0.47
Modular Programming for Microcontrollers	-0.44
Watchdog configuration on Stellaris Launchpad LM4F120	-2.11
VHDL - Assigning Default Values	+0.02
VHDL - Design Library Does Not Contain Unit	0.00
Why do we use functions in VHDL	+0.44
Converting 8 bit bmp to halftone bmp	+0.23
State management in VHDL FSMs	-0.27
How to build FSM when there are too many states?	-1.80
Double buffering on lpc1788	-0.02
How can I read binary data in VHDL/modelsim whithout using special...	+0.47
Sum of Array elements VHDL	0.00
how to do a left shift in Modelsim in order to built a booth multip...	0.00
Is process in VHDL reentrant?	-0.51
Connect components without signals	-0.28
When to use "case" and when to use "with select"	-0.04
for loop Arduino/C	+0.17
what is the best way to exchange 2 registers in Verilog	-0.29
How to index a std_logic_vector by enumeration	-0.52
VHDL Entity not executing in simulator with unassigned 'U' inputs	0.00
how to handle -- fast tx & recepion of data --- device driver L...	-0.03
VHDL syntax to drop multiplication remainder	-0.03
Design tips for synchronising signals through a VHDL pipeline	+0.78
Microblaze Cross Compile	0.00
Reverse bit order on VHDL	0.00
ODDR2 usage found in auto-generated xilinx wrapper VHDL file	+0.48
How to represent Integer greater than integer'high	-0.37
How to to create include files in vhdl?	-0.38
VHDL - creating a variable number of signals	-0.48
how to compare an integer and an std_logic vector	+0.01
"unsigned" type conversion demands input in sequential pr...	+0.48
VHDL - Successive Approximation Register	-0.02
Implementing delay in VHDL state machine	0.00