StackRating

An Elo-based rating system for Stack Overflow

Home | About | Stats and Analysis | Get a Badge

Rating Stats for

Martin Thompson

Rating
1487.04 (4,454,104th)

Reputation
14,667 (9,652nd)

Page: 1 2 3 4 5 6 ... 12

Title	Δ
Check every element of array of record is 0 in VHDL	+0.52
getting undefined symbol error, even thought the variable is define...	-0.51
Partial FPGA reconfiguration and performance	0.00
How to simulate an external piece of hardware during the developmen...	0.00
Define "enum"-type depending on generics	-0.52
Data compression for FPGA bitstream	-1.83
How to create derived types of abstract data types in VHDL 2008?	-0.01
How to typecast integer to unsigned in VHDL	-0.01
VHDL / How to initialize my signal?	-1.55
Synplify prunes my register when I use to_integer to access a Const...	0.00
ModelSim VHDL real simulation time estimation	0.00
Managing serial conversation between Linux and Arduino	-0.01
Run and increment a counter in VHDL	0.00
dma for FPGA based PCI IO card	0.00
How to display a 14 bit output onto a 2 digit display?	-0.52
Generate random values in VHDL function	+0.49
stm32f405 generate trigger signal pwm	0.00
FIFO with 2 clocks in VHDL	+0.48
Reading from FTDI sync FT245 FIFO returns zero bytes	-0.01
Verilog accessing memory address	-0.04
Communication between processes in VHDL	0.00
Run multiple processes in VHDL	+0.29
Generic Records (vhdl2008)	0.00
XOR using a 4:1 Mux in VHDL	-0.02
VHDL initialize vector (the length is not a multiple of 4) in hex	-0.52
What minimal files needed for Microblaze rebuild	+0.49
I don't understand what's wrong with this VHDL code?	+0.59
Is it possible to convert an inout signal to two signals (in and ou...	0.00
SPI data transfer - why MOSI goes to zero half cycle before the dat...	0.00
8 bit ALU for microprocessor	-0.04
Generic Records (attempted via vhdl 2008 generic package)	0.00
Modelsim not recognizing an architecture including "case...whe...	0.00
Reading and Writing to a file simultaneously	0.00
VHDL: on converting numbers? real to std_logic_vector	+0.47
What is a ethernet frame sample which can be sent?	0.00
Is is possible to simultaneously use Arduino serial monitor while r...	-0.00
How are loops within a process synthesized in VHDL?	-0.01
Programming EP2C35F672C6 FPGA purchased	0.00
Multiple Processes on Microchip PIC32 Ethernet Starter Kit	+1.52
VHDL programming	-0.02
Mealy and Moore implementations in verilog	+0.48
When to use what types	-0.02
Can I visually separate bits inside bit vector constants?	-0.51
Need to improve the Linux performance for embedded system	-0.51
Fading Arduino RGB LED from one color to the other?	-0.02
Brightness on digital output varies based on level input type	-0.51
Generating multiple product firmwares from single codebase using c2...	0.00
What are examples of FPGA or ASIC clusters outside of Bitcoin?	+0.47
Clarification on Ethernet, MII, SGMII, RGMII and PHY	0.00
array and multiplexer in Verilog	+0.39