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Rating Stats for

Martin Thompson

Rating
1487.04 (4,454,104th)

Reputation
14,667 (9,652nd)

Page: 1 2 3 4 5 ... 12

Title	Δ
Making a clock divider	+0.03
Compiling *.vhdl into a library, using Altera Quartus II	+0.02
Controlling an LCD in VHDL on spartan 6	-0.54
what is #define equivalent in VHDL	-0.47
nbit Bitslice ALU with For/IF Generate in VHDL	+0.42
VHDL signal dimension issue when reducing a generic value down to 0	-1.66
Why does this example from the myHDL manual give me different resul...	0.00
VHDL state machine differences (for synthesization)	-0.43
Using variables in case statement, VHDL	+0.23
Case statement within a case statement	-0.01
VHDL sequencer: incrementing output sigals in FSM	-0.51
Why does compiling C take so long time?	-0.51
Custom External Ports not showing on custom IP Core - Zedboard	0.00
convert a std_logic_vector INPUT to IEEE Float type	+0.59
How to use the memory of the Xilinx-FPGA Virtex5/7 as a memory mapp...	0.00
synthesis of dynamic mux on std_logic_vector bytes	-0.44
How to output array elements in random order using VHDL	+0.32
VHDL Error std_logic type does not match integer literal	-0.01
Comparing a long std_logic_vector to zeros	+0.31
How to design a variable bit (m bit) counter using VHDL or Verilog?	+2.02
Bit shift register vhdl varying size	0.00
How can I have two different "processes" for the same ent...	+0.00
VHDL: enumeration type minimal dimension	-0.10
py2exe error handling redirection and popup	0.00
Alternative way to implement state machines in VHDL	-0.25
Can a PORT MAP be done in VHDL package body?	-0.26
Why use concurrent statements in VHDL?	-0.43
How to find out the value of 1 iteration in microblaze	0.00
Creating a cache memory benchmark in VHDL	+0.59
Polling with C and assembly for Nios 2	0.00
Creating a vector with other vector`s index as elements in VHDL	+0.03
VHDL initialize variable to multiple values	-0.51
Transfer data using NDIS	0.00
Compile Date and Time in FPGA	-0.24
Acceleration PHP with FPGA and GPU	0.00
vhdl bitwise operation on vector	0.00
Function with don't-care inputs	-0.24
VHDL - How should I create a clock in a testbench?	+0.09
Changing the bit depth of audio with VHDL to use a codec	0.00
VHDL component and outputs based on generic	+0.49
If Statement for reduction of a 9-bit to 5-bit binary number	+0.19
testbench help to make one clock cycle delay	-0.48
Is conversion from OpenCV code to FPGA code is easier than Matlab c...	+0.49
Adjusting the operating frequency of a module in Verilog	0.00
Why do I need the mask instruction?	0.00
VHDL - determining the range of a 2d array	-0.49
Xillinx UART Rx on Spartan-3E	0.00
Is it bad if all variables are defined as volatile on AVR programmi...	+0.16
FPGA netlist parser	+0.48
How to convert 8 bits to 16 bits in VHDL?	-0.47