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Rating Stats for

Martin Thompson

Rating
1487.04 (4,454,104th)

Reputation
14,667 (9,652nd)

Page: 1 2 3 4 ... 12

Title	Δ
i want a synthesizable code to save the output in a file in verilog...	+0.03
How is a JTAG used as a debugger?	+2.04
Error (10028): Can't resolve multiple constant drivers for net... V...	-0.50
Store std_logic bits in ascending order into a large array	-1.22
No function declarations for operator + error in VHDL	-0.06
Unintentional latches in finite state machine (VHDL) + feedback	+0.52
Why is rising edge prefered over falling edge	+0.36
How to Transfer Array Data in VHDL?	+0.49
4 bit U/D counter in VHDL	+0.50
resetting values in a VHDL register and stop writing further	0.00
All values changes in array using vhdl	0.00
VHDL error 10500 concerning syntax with an if statement	-0.50
VHDL writing std_logic_vector as a signed integer in file	-0.50
synchronous state machine VHDL	+0.51
VHDL, Multiple reset counter	-0.01
Too many comps of type "BUFGMUX" found to fit this device...	-0.52
What is the correct implementation of handling asynchronous signals...	-0.21
how many processes i need to monitor two signals?	0.00
How to manage large VHDL testbenches	-0.46
c++ Fade between colors? (Arduino)	+0.04
change signal inside a process with if statement - VHDL	+0.50
Get a modules data without an entity statement in VHDL?	-0.45
Breaking out of a procedure in VHDL	-0.50
Two's complement VHDL	+0.25
Error with wait conditions	-0.46
Generics in hardware description language	-0.22
Time stamp in VHDL	-0.01
Default values of RAM	0.00
how to approach string/pattern checking in VHDL?	+0.03
Whats the meaning of this" vector(vector'HIGH)='1'"?	-0.12
How do I fill in an FPGA generated circle in verilog for synthesis...	-0.49
Xilinx SDK (Eclipse) project command line build	+0.00
Which algorithm should I use for car's head/tail light detection in...	0.00
Hardware implementation for integer data processing	0.00
VHDL - Adding two 8-bit vectors into a 9-bit vector	+0.00
"template" VHDL entities	+0.03
Identifying a start of a frame	0.00
Why int is preffered rather than (unsigned) char for small integers...	-1.05
Console output is not aligned	-0.75
VHDL, Can a clocked process introduce latches?	-0.81
Floating Point Adder - Optimization of comparator	+0.00
Global Placement Phase 8.8 Running Indefinitely, Xilinx	-0.83
How to use a constant calculated from generic parameter in a port d...	+0.15
For loop, arrays, step motor VHDL	-0.59
Evaluate if a value is increasing or decreasing (arduino)	-0.25
VGA VHDL Screen Moves when I refresh	+0.00
Comparing integer and binary in VHDL	+0.26
Writing a Register File in VHDL	-0.45
Changing IF statements, saving some code	-0.50
VHDL Can you declare a package and an entity in the same file?	-0.41